ChipFind - документация

Электронный компонент: 100350PC

Скачать:  PDF   ZIP
2000 Fairchild Semiconductor Corporation
DS009884
www.fairchildsemi.com
July 1988
Revised August 2000
1
00350 Low
Power Hex
D-
T
y
pe
La
tch
100350
Low Power Hex D-Type Latch
General Description
The 100350 contains six D-type latches with true and com-
plement outputs, a pair of common Enables (E
a
and E
b
),
and a common Master Reset (MR). A Q output follows its D
input when both E
a
and E
b
are LOW. When either E
a
or E
b
(or both) are HIGH, a latch stores the last valid data
present on its D input before E
a
or E
b
went HIGH. The MR
input overrides all other inputs and makes the Q outputs
LOW. All inputs have 50 k
pull-down resistors.
Features
s
20% power reduction of the 100150
s
2000V ESD protection
s
Pin/function compatible with 100150
s
Voltage compensated operating range
=
-
4.2V to
-
5.7V
Ordering Code:
Devises also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagrams
24-Pin DIP
28-Pin PLCC
Order Number
Package Number
Package Description
100350PC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100350QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Pin Names
Description
D
0
D
5
Data Inputs
E
a
, E
b
Common Enable Inputs (Active LOW)
MR
Asynchronous Master Reset Input
Q
0
Q
5
Data Outputs
Q
0
Q
5
Complementary Data Outputs
www.fairchildsemi.com
2
100350
Truth Tables
(Each Latch)
Latch Operation
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Don't Care
Note 1: Retains data present before E positive transition
Asynchronous Operation
Logic Diagram
Inputs
Outputs
D
n
E
a
E
b
MR
Q
n
L
L
L
L
L
H
L
L
L
H
X
H
X
L
Latched (Note 1)
X
X
H
L
Latched (Note 1)
Inputs
Outputs
D
n
E
a
E
b
MR
Q
n
X
X
X
H
L
3
www.fairchildsemi.com
1
00350
Absolute Maximum Ratings
(Note 2)
Above which the useful life may be impaired.
Recommended Operating
Conditions
Note 2: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Note 3: ESD testing conforms to MIL-STD-883, Method 3015.
DC Electrical Characteristics
(Note 4)
V
EE
=
-
4.5V to
-
5.7V, V
CC
=
V
CCA
=
GND, T
C
=
0
C to
+
85
C
Note 4: The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under "worst case" conditions.
DIP AC Electrical Characteristics
V
EE
=
-
4.2V to
-
5.7V, V
CC
=
V
CCA
=
GND
Storage Temperature (T
STG
)
-
65
C to
+
150
C
Maximum Junction Temperature (T
J
)
+
150
C
V
EE
Pin Potential to Ground Pin
-
7.0V to
+
0.5V
Input Voltage (DC)
V
EE
to
+
0.5V
Output Current (DC Output HIGH)
-
50 mA
ESD (Note 3)
2000V
Case Temperature (T
C
)
0
C to
+
85
C
Supply Voltage (V
EE
)
-
5.7V to
-
4.2V
Symbol
Parameter
Min
Typ
Max
Units
Conditions
V
OH
Output HIGH Voltage
-
1025
-
955
-
870
mV
V
IN
=
V
IH (Max)
Loading with
V
OL
Output LOW Voltage
-
1830
-
1705
-
1620
or V
IL (Min)
50
to
-
2.0V
V
OHC
Output HIGH Voltage
-
1035
mV
V
IN
=
V
IH (Min)
Loading with
V
OLC
Output LOW Voltage
-
1610
or V
IL (Max)
50
to
-
2.0V
V
IH
Input HIGH Voltage
-
1165
-
870
mV
Guaranteed HIGH Signal for All Inputs
V
IL
Input LOW Voltage
-
1830
-
1475
mV
Guaranteed LOW Signal for All Inputs
I
IL
Input LOW Current
0.50
A
V
IN
=
V
IL (Min)
I
IH
Input HIGH Current
MR
240
D
n
240
A
V
IN
=
V
IH (Max)
E
a
, E
b
240
I
EE
Power Supply
Inputs Open
Current
-
89
-
44
mA
V
EE
=
-
4.2V to
-
4.8V
-
93
-
44
V
EE
=
-
4.2V to
-
5.7V
Symbol
Parameter
T
C
=
0
C
T
C
=
+
25
C
T
C
=
+
85
C
Units
Conditions
Min
Max
Min
Max
Min
Max
t
PLH
Propagation Delay
Figures 1, 2
t
PHL
D
n
to Output
0.50
1.40
0.50
1.40
0.50
1.50
ns
(Transparent Mode)
t
PLH
Propagation Delay
0.75
1.85
0.75
1.85
0.75
2.05
ns
t
PHL
E
a
, E
b
to Output
t
PLH
Propagation Delay
0.90
2.10
0.90
2.10
0.90
2.10
ns
Figures 1, 3
t
PHL
MR to Output
t
TLH
Transition Time
0.35
1.30
0.35
1.30
0.35
1.30
ns
Figures 1, 2
t
THL
20% to 80%, 80% to 20%
t
S
Setup Time
Figures 3, 4
D
0
D
5
1.00
1.00
1.00
ns
MR (Release Time)
1.60
1.60
1.60
t
H
Hold Time, D
0
D
5
0.40
0.40
0.40
ns
Figure 4
t
PW
(L)
Pulse Width LOW
2.00
2.00
2.00
ns
Figure 2
E
a
, E
b
t
PW
(H)
Pulse Width HIGH, MR
2.00
2.00
2.00
ns
Figure 3
www.fairchildsemi.com
4
100350
PLCC AC Electrical Characteristics
V
EE
=
-
4.2V to
-
5.7V, V
CC
=
V
CCA
=
GND
Test Circuit
Note:
V
CC
, V
CCA
=
+
2V, V
EE
=
-
2.5V
L1 and L2
=
equal length 50
impedance lines
R
T
=
50
terminator internal to scope
Decoupling 0.1
F from GND to V
CC
and V
EE
All unused outputs are loaded with 50
to GND
C
L
=
Fixture and stray capacitance
3 pF
FIGURE 1. AC Test Circuit
Symbol
Parameter
T
C
=
0
C
T
C
=
+
25
C
T
C
=
+
85
C
Units
Conditions
Min
Max
Min
Max
Min
Max
t
PLH
Propagation Delay
Figures 1, 2
t
PHL
D
n
to Output
0.50
1.20
0.50
1.20
0.50
1.30
ns
(Transparent Mode)
t
PLH
Propagation Delay
0.75
1.65
0.75
1.65
0.75
1.85
ns
t
PHL
E
a
, E
b
to Output
t
PLH
Propagation Delay
0.90
1.90
0.90
1.90
0.90
1.90
ns
Figures 1, 3
t
PHL
MR to Output
t
TLH
Transition Time
0.35
1.10
0.35
1.10
0.35
1.10
ns
Figures 1, 2
t
THL
20% to 80%, 80% to 20%
t
S
Setup Time
Figures 3, 4
D
0
D
5
0.90
0.90
0.90
ns
MR (Release Time)
1.50
1.50
1.50
t
H
Hold Time, D
0
D
5
0.30
0.30
0.30
ns
Figure 4
t
PW
(L)
Pulse Width LOW
2.00
2.00
2.00
ns
Figure 2
E
a
, E
b
t
PW
(H)
Pulse Width HIGH, MR
2.00
2.00
2.00
ns
Figure 3
5
www.fairchildsemi.com
1
00350
Switching Waveforms
FIGURE 2. Enable Timing
FIGURE 3. Reset Timing
Notes:
t
S
is the minimum time before the transition of the enable that information must be present at the data input.
t
H
is the minimum time after the transition of the enable that information must remain unchanged at the data input.
FIGURE 4. Data Setup and Hold Time