1999 Fairchild Semiconductor Corporation
DS010650
www.fairchildsemi.com
February 1990
Revised November 1999
1
00393 Low
Power 9-Bi
t ECL-t
o
-TTL
T
r
anslat
or wit
h
La
tches
100393
Low Power 9-Bit ECL-to-TTL Translator with Latches
General Description
The 100393 is a 9-bit translator for converting F100K logic
levels to TTL logic levels. A LOW on the latch enable (LE)
latches the data at the input state. A HIGH on the LE
makes the latches transparent. A HIGH on either the ECL
or TTL output enable (OE ECL or OE TTL), holds the out-
puts in a high impedance state.
The 100393 is designed with TTL, 64 mA outputs for Bus
Driving capability. All ECL inputs have 50 k
pull-down
resistors. When the inputs are either unconnected or at the
same potential, the outputs will go LOW.
Features
s
64 mA I
OL
drive capability
s
2000V ESD protection
s
-
4.2V to
-
5.7V operating range
s
Latched outputs
s
TTL outputs
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagram
Order Number
Package Number
Package Description
100393QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Pin Names
Description
D
0
D
8
Data Inputs (ECL)
Q
0
Q
8
Data Outputs (TTL)
LE
Latch Enable Input (ECL)
OE TTL
Output Enable (TTL)
OE ECL
Output Enable (ECL)
3
www.fairchildsemi.com
1
00393
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
DC Electrical Characteristics
(Note 3)
V
EE
=
-
4.2V to
-
5.7V; V
CC
=
V
CCA
=
GND, V
TTL
=
+
4.5V to
+
5.5V, T
C
=
0
C to
+
85
C
Note 3: The specified limits represent the "worst case" value for the parameter. Since these "worst case" values normally occur at the temperature extremes,
additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the
tables are chosen to guarantee operation under "worst case" conditions.
Storage Temperature (T
STG
)
-
65
C to
+
150
C
Maximum Junction Temperature (T
J
)
+
150
C
Case Temperature under Bias (T
C
)
0
C to
+
85
C
V
EE
Pin Potential to Ground Pin
-
7.0V to
+
0.5V
V
TTL
Pin Potential to Ground Pin
-
0.5V to
+
6.0V
ECL Input Voltage (DC)
V
EE
to
+
0.5V
TTL Input Voltage
-
0.5V to
+
7.0V
Output Current (DC Output HIGH)
+
130 mA
ESD (Note 2)
2000V
Case Temperature (T
C
)
0
C to
+
85
C
Supply Voltage
V
EE
-
5.7V to
-
4.2V
V
TTL
+
4.5V to
+
5.5V
Symbol
Parameter
Min
Typ
Max
Units
Conditions
V
OH
Output HIGH Voltage
2.5
V
I
OH
=
-
1 mA
V
IN
=
V
IL
(Min) or
2.0
I
OH
=
-
15 mA
V
IH
(Max)
V
OL
Output LOW Voltage
0.55
V
I
OL
=
64 mA
V
IN
=
V
IL
(Min) or
0.50
I
OL
=
24 mA
V
IH
(Max)
V
IH
Input HIGH Voltage
ECL Inputs
-
1165
-
870
mV
Guaranteed HIGH Signal for All Inputs
OE TTL
2.0
V
V
IL
Input LOW Voltage
ECL Inputs
-
1830
-
1475
mV
Guaranteed LOW Signal for All Inputs
OE TTL
0.8
V
I
BVI
Input Breakdown Current
10
A
V
BI
=
7.0V
I
IH
ECL Input HIGH Current
ECL Inputs
240
A
V
IN
=
V
IH
(Max)
OE ECL
350
TTL Input HIGH Current
OE TTL
5.0
A
V
IN
=
2.7V
I
IL
ECL Input LOW Current
ECL Inputs
0.5
A
V
IN
=
V
IL
(Min)
TTL Input LOW Current
OE TTL
-
50
A
V
IN
=
0.5V
I
CEX
Output HIGH Leakage Current
250
A
I
OS
Output Short-Circuit Current
-
100
-
225
mA
V
OUT
=
0.0V, V
TTL
=
+
5.5V
I
OZH
3-STATE Current Output HIGH
+
50
A
V
OUT
=
+
2.7V
I
OZL
3-STATE Current Output LOW
-
50
A
V
OUT
=
0.5V
V
FCD
Input Clamp Diode Voltage
-
1.2
V
I
IN
=
-
18 mA
I
EE
V
EE
Power Supply Current
-
39
-
18
mA
Inputs OPEN
I
CCH
V
TTL
Power Supply Current HIGH
29
mA
I
CCL
V
TTL
Power Supply Current LOW
65
mA
I
CCZ
V
TTL
Power Supply Current
49
mA
3-STATE
5
www.fairchildsemi.com
1
00393
Switching Waveforms
FIGURE 2. Propagation Delays, Setup and Hold Times, and Pulse Width
FIGURE 3. Enable and Disable Waveforms, OE TTL
FIGURE 4. Enable and Disable Waveforms, OE ECL
PDF 
ZIP
