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Электронный компонент: 100398QI

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2000 Fairchild Semiconductor Corporation
DS010970
www.fairchildsemi.com
February 1992
Revised August 2000
1
00398 Q
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ad

Di
ff
erent
i
al

ECL/
TTL T
r
ansl
ati
ng T
r
ansc
eiver

wi
th Latch
100398
Quad Differential ECL/TTL Translating Transceiver
with Latch
General Description
The 100398 is a quad latched transceiver designed to con-
vert TTL logic levels to differential F100K ECL logic levels
and vice versa. This device was designed with the capabil-
ity of driving a differential 25
ECL load with cutoff capabil-
ity, and will sink a 64 mA TTL load. The 100398 is ideal for
mixed technology applications utilizing either an ECL or
TTL backplane.
The direction of translation is set by the direction control
pin (DIR). The DIR pin on the 100398 accepts TTL logic
levels. A TTL LOW on DIR sets up the ECL pins as inputs
and TTL pins as outputs. A TTL HIGH on DIR sets up the
TTL pins as inputs and ECL pins as outputs.
A LOW on the output enable input pin (OE) holds the ECL
output in a cut-off state and the TTL outputs at a high
impedance level. A HIGH on the latch enable input (LE)
latches the data at both inputs even though only one output
is enabled at the time. A LOW on LE makes the latch trans-
parent.
The cut-off state is designed to be more negative than a
normal ECL LOW level. This allows the output emitter-fol-
lowers to turn off when the termination supply is
-
2.0V, pre-
senting a high impedance to the data bus. This high
impedance reduces termination power and prevents loss of
low state noise margin when several loads share the bus.
The 100398 is designed with FAST
TTL output buffers,
featuring optimal DC drive and capable of quickly charging
and discharging highly capacitive loads. All Inputs have
50 k
pull-down resistors.
Features
s
Differential ECL input/output structure
s
64 mA FAST TTL outputs
s
25
differential ECL outputs with cut-off
s
Bi-directional translation
s
2000V ESD protection
s
Latched outputs
s
3-STATE outputs
s
Voltage compensated operating range
=
-
4.2V to
-
5.7V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
FAST
is a registered trademark of Fairchild Semiconductor.
Order Number
Package Number
Package Description
100398PC
N24E
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100398QC
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100398QI
V28A
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (
-
40
C to
+
85
C)
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2
100398
Logic Symbol
Connection Diagrams
24-Pin DIP
28-Pin PLCC
Pin Descriptions
Truth Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Don't Care
Z
=
High Impedance
Note 1: ECL input to TTL output mode.
Note 2: TTL input to ECL output mode.
Note 3: Retains data present before LE set HIGH.
Note 4: Latch is transparent.
Pin Names
Description
E
0
E
3
ECL Data I/O
E
0
E
3
Complementary ECL
Data I/O
T
0
T
3
TTL Data I/O
OE
Output Enable Input Levels
LE
Latch Enable Input Levels
DIR
Direction Control
Input (TTL levels)
GNDECL
ECL Ground
GNDECLO
ECL Output Ground
GNDS
ECL Ground-to-Substrate
V
EE
ECL Quiescent Power Supply
V
EED
ECL Dynamic Power Supply
GNDTTL
TTL Quiescent Ground
GNDTTLD
TTL Dynamic Ground
V
TTL
TTL Quiescent Power Supply
V
TTLD
TTL Dynamic Power Supply
LE
DIR
OE
ECL
TTL
Notes
Port
Port
0
0
0
LOW
Z
(Cut-Off)
0
0
1
Input
Output (Note 1)(Note 4)
0
1
0
LOW
Z
(Cut-Off)
0
1
1
Output
Input
(Note 2)(Note 4)
1
0
0
Input
Z
(Note 1)(Note 3)
1
0
1
Latched
X
(Note 1)(Note 3)
1
1
0
Low
Input
(Note 2)(Note 3)
(Cut-Off)
1
1
1
Latched
X
(Note 2)(Note 3)
3
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1
00398
Functional Diagram
Note: LE, and OE use TTL logic levels
Detail
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4
100398
Absolute Maximum Ratings
(Note 5)
Recommended Operating
Conditions
Note 5: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Note 6: The specified limits represent the "worst case" value for the param-
eter. Since these values normally occur at the temperature extremes, addi-
tional noise immunity and guardbanding can be achieved by decreasing the
allowable system operating ranges. Conditions for testing shown in the
tables are chosen to guarantee operation under "worst case" conditions.
Note 7: ESD testing conforms to MIL-STD-883, Method 3015.
Commercial Version
TTL-to-ECL DC Electrical Characteristics
(Note 9)
V
EE
=
-
4.2V to
-
5.7V, GND
=
0V, T
C
=
0
C to
+
85
C, V
TTL
=
+
4.5V to
+
5.5V
Note 8: Either voltage limit or current limit is sufficient to protect inputs.
Note 9: The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under "worst case" conditions.
Storage Temperature (T
STG
)
-
65
C to
+
150
C
Maximum Junction Temperature
(T
J
)
+
150
C
V
EE
Pin Potential to Ground Pin
-
7.0V to
+
0.5V
V
TTL
Pin Potential to Ground Pin
-
0.5V to
+
6.0V
ECL Input Voltage (DC)
V
EE
to
+
0.5V
ECL Output Current
(DC Output HIGH)
-
50 mA
TTL Input Voltage (Note 6)
-
0.5V to
+
7.0V
TTL Input Current (Note 6)
-
30 mA to
+
5.0 mA
Voltage Applied to Output in
HIGH State 3-STATE Output
-
0.5V to
+
5.5V
Current Applied to TTL
Output in LOW State (Max)
twice the Rated I
OL
(mA)
ESD (Note 7)
2000V
Case Temperature (T
C
)
Commercial
0
C to
+
85
C
Industrial
-
40
C to
+
85
C
ECL Supply Voltage (V
EE
)
-
5.7V to
-
4.2V
TTL Supply Voltage (V
TTL
)
+
4.5V to
+
5.5V
Symbol
Parameter
Min
Typ
Max
Units
Conditions
V
OH
Output HIGH Voltage
-
1025
-
955
-
870
mV
V
IN
=
V
IH(Max)
or V
IL(Min)
V
OL
Output LOW Voltage
-
1830
-
1705
-
1620
mV
Loading with 50
to
-
2V
Cutoff Voltage
-
2000
-
1950
mV
OE and LE LOW, DIR HIGH
V
IN
=
V
IH(Max)
or V
IL
(Min),
Loading with 50
to
-
2V
V
OHC
Output HIGH Voltage
-
1035
mV
Corner Point High
V
IN
=
V
IH(Min)
or V
IL(Max)
V
OLC
Output LOW Voltage
-
1610
mV
Loading with 50
to
-
2V
Corner Point Low
V
IH
Input HIGH Voltage
2.0
5.0
V
Over V
TTL
, V
EE
, T
C
Range
V
IL
Input LOW Voltage
0
0.8
V
Over V
TTL
, V
EE
, T
C
Range
I
IH
Input HIGH Current
5.0
A
V
IN
=
+
2.7V
Breakdown Test
0.5
mA
V
IN
=
+
5.5V
I
IL
Input LOW Current
-
700
A
V
IN
=
+
0.5V
V
FCD
Input Clamp
-
1.2
V
I
IN
=
-
18 mA
Diode Voltage
I
EE
V
EE
Supply Current
-
99
-
50
mA
LE LOW, OE and DIR HIGH
Inputs Open
I
EEZ
V
EE
Supply Current
-
159
-
90
mA
LE and OE LOW, DIR HIGH
Inputs Open
5
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1
00398
Commercial Version
(Continued)
ECL-to-TTL DC Electrical Characteristics
(Note 10)
V
EE
=
-
4.2V to
-
5.7V, GND
=
0V, T
C
=
0
C to
+
85
C, C
L
=
50 pF, V
TTL
=
+
4.5V to
+
5.5V
Note 10: The specified limits represent the "worst case" value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under "worst case" conditions.
DIP and PCC TTL-to-ECL AC Electrical Characteristics
V
EE
=
-
4.2V to
-
5.7V, V
TTL
=
+
4.5V to
+
5.5V
Symbol
Parameter
Min
Typ
Max
Units
Conditions
V
OH
Output HIGH Voltage
2.7
3.1
V
I
OH
=
-
3 mA, V
TTL
=
4.75V
2.4
2.9
V
I
OH
=
-
3 mA, V
TTL
=
4.50V
V
OL
Output LOW Voltage
0.3
0.5
V
I
OL
=
24 mA, V
TTL
=
4.50V
V
IH
Input HIGH Voltage
-
1165
-
870
mV
Guaranteed HIGH Signal for All Inputs
V
IL
Input LOW Voltage
-
1830
-
1475
mV
Guaranteed LOW Signal for All Inputs
V
DIFF
Input Voltage Differential
150
mV
Required for Full Output Swing
V
CM
Common Mode Voltage
GNDECL
-
2.0
GNDECL
-
0.5
V
I
IH
Input HIGH Current
30
A
V
IN
=
V
IH
(Max)
I
IL
Input LOW Current
0.50
A
V
IN
=
V
IL
(Min)
I
OZHT
3-STATE Current Output High
70
A
V
OUT
=
+
2.7V
I
OZLT
3-STATE Current Output Low
-
650
A
V
OUT
=
+
0.5V
I
OS
Output Short-Circuit Current
-
100
-
225
mA
V
OUT
=
0.0V, V
TTL
=
+
5.5V
I
CEX
Output HIGH Leakage Current
50
A
V
OUT
=
5.5V
I
ZZ
Bus Drainage Test
500
A
V
OUT
=
5.25V
I
TTL
V
TTL
Supply Current
39
mA
TTL Outputs LOW
27
mA
TTL Outputs HIGH
39
mA
TTL Outputs in 3-STATE
Symbol
Parameter
T
C
=
0
C
T
C
=
25
C
T
C
=
85
C
Units
Conditions
Min
Max
Min
Max
Min
Max
f
MAX
Toggle Frequency
180
180
180
MHz
t
PLH
T
n
to E
n
, E
n
0.90
2.10
0.80
2.20
0.70
2.50
ns
Figures 1, 3
t
PHL
(Transparent)
t
PLH
LE to E
n
, E
n
1.40
2.70
1.50
2.70
1.80
3.10
ns
Figures 1, 3
t
PHL
t
PZH
OE to E
n
, E
n
2.90
8.00
2.80
6.90
2.80
5.80
ns
Figures 1, 3
(Cutoff to HIGH)
t
PHZ
OE to E
n
, E
n
1.30
2.70
1.40
2.90
1.70
3.40
ns
Figures 1, 3
(HIGH to Cutoff)
t
PHZ
DIR to E
n
, E
n
1.30
2.70
1.40
2.90
1.80
3.50
ns
Figures 1, 3
(HIGH to Cutoff)
t
S
T
n
to LE
0.70
0.70
0.70
ns
Figures 1, 3
t
H
T
n
to LE
0.90
0.80
0.70
ns
Figures 1, 3
t
TLH
Transition Time
0.45
1.50
0.45
1.50
0.45
1.50
ns
Figures 1, 3
t
THL
20% to 80%, 80% to 20%