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Электронный компонент: 100LVELT22

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2003 Fairchild Semiconductor Corporation
DS500777
www.fairchildsemi.com
January 2003
Revised January 2003
1
00L
V
E
L
T
22 3.
3V
Dual

L
V
TTL/
L
V
CM
OS to Dif
f
er
enti
al L
VPECL
T
r
ansla
t
or
100LVELT22
3.3V Dual LVTTL/LVCMOS to
Differential LVPECL Translator
General Description
The 100LVELT22 is a LVTTL/LVCMOS to differential
LVPECL translator operating from a single
+
3.3V supply.
Both outputs of a differential pair should be terminated in
50
to V
CC
- 2.0V even if only one output is being used. If
an output pair is unused both outputs can be left open
(un-terminated).
The 100 series is temperature compensated.
Features
s
Typical propagation delay of 350 ps
s
<
100 ps skew between outputs
s
Max I
CC
of 28 mA at 25
C
s
When TTL input is left Open Q output defaults HIGH
s
Fairchild MSOP-8 package is a drop-in replacement to
ON TSSOP-8
s
Flow through pinout
s
Meets or exceeds JEDEC specification EIA/JESD78 IC
latch-up test
s
Moisture Sensitivity Level 1
s
ESD Performance:
Human Body Model
>
2000V
Machine Model
>
200V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Top View
Pin Descriptions
Logic Diagram
Order Number
Product
Package Description
Package
Code
Number
Top Mark
100LVELT22M
M08A
KVT22
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
100LVELT22M8
(Preliminary)
MA08D
KR22
8-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide
Pin Name
Description
Q
n
, Q
n
LVPECL Differential Outputs
D
0
, D
1
LVTTL/LVCMOS Inputs
V
CC
Positive Supply
GND
Ground
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2
100L
VE
L
T22
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
LVPECL DC Electrical Characteristics
V
CC
=
3.3V; GND
=
0.0V (Note 2)
Note 2: Output parameters vary 1 to 1 with V
CC
. V
CC
can vary
0.15V.
Note 3: Outputs are terminated through a 50
resistor to V
CC
-
2.0V.
Note: Devices are designed to meet the DC specifications after thermal equilibrium has been established. Circuit is tested with air flow greater than
500LFPM maintained.
LVTTL/LVCMOS DC Electrical Characteristics
V
CC
=
3.3V; GND
=
0.0V (Note 4)
Note 4: V
CC
can vary
0.15V.
Note: Devices are designed to meet the DC specifications after thermal equilibrium has been established. Circuit is tested with air flow greater than
500LFPM maintained.
AC Electrical Characteristics
V
CC
=
3.3V; GND
=
0.0V (Note 5)
Note 5: V
CC
can vary
0.15V.
Note 6: Specifications for standard LVTTL input signal (see Figure 1).
Supply Voltage (V
CC
)
0.0V to
+
7.0V
Input Voltage (V
I
) V
I
V
CC
0.0V to
+
7.0V
DC Output Current (I
OUT
)
Continuous
50 mA
Surge
100 mA
Storage Temperature (T
STG
)
-
65
C to
+
150
C
Power Supply Operating
V
CC
=
3.0V to 3.8V
LVTTL/LVCMOS Input Voltage
0.0V to V
CC
Free Air Operating Temperature (T
A
)
-
40
C to
+
85
C
Symbol
Parameter
-
40
C
25
C
85
C
Units
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
I
CC
Power Supply Current
28
28
29
mA
V
OH
Output HIGH Voltage (Note 3)
2215
2420
2275
2420
2275
2420
mV
V
OL
Output LOW Voltage (Note 3)
1470
1745
1490
1680
1490
1680
mV
Symbol
Parameter
T
A
=
-
40
C to 85
C
Units
Condition
Min
Typ
Max
I
IH
Input HIGH Current
20
A
V
IN
=
2.7V
100
V
IN
=
V
CC
I
IL
Input LOW Current
-
200
A
V
IN
=
0.5V
V
IK
Clamp Diode Voltage
-
1.2
V
I
IN
=
-
18 mA
V
IH
Input HIGH Voltage
2.0
V
V
IL
Input LOW Voltage
0.8
V
Symbol
Parameter
-
40
C
25
C
85
C
Units
Figure
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Number
f
MAX
Maximum Toggle Frequency
TBD
TBD
TBD
MHz
t
JITTER
Cycle-to-Cycle Jitter
TBD
TBD
TBD
ps
t
PLH
/ t
PHL
Propagation Delay (Note 6)
200
350
600
200
350
600
200
350
600
ps
Figure 1
t
SKEW
Skew
Output-to-Output
30
100
30
100
30
100
ps
Part-to-Part
400
400
400
t
r
, t
f
Output Rise Time Q (20% to 80%)
200
550
200
500
200
500
ns
Figure 2
3
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1
00L
V
E
L
T
22
Switching Waveforms
FIGURE 1. LVTTL to Differential LVPECL Propagation Delay
FIGURE 2. Differential Output Edge Rates
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4
100L
VE
L
T22
Physical Dimensions
inches (millimeters) unless otherwise noted
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M08A
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
5
www.fairchildsemi.com
1
00L
V
E
L
T
22 3.
3V
Dual

L
V
TTL/
L
V
CM
OS to Dif
f
er
enti
al L
VPECL
T
r
ansla
t
or
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
8-Lead Molded Small Outline Package (MSOP), JEDEC MO-187, 3.0mm Wide
Package Number MA08D
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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