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Электронный компонент: 203N

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September 2005
2004 Fairchild Semiconductor Corporation
FDZ203N Rev. E6(W)
FDZ203N
N-Channel 2.5V Specified PowerTrench
BGA MOSFET
General Description
Combining Fairchild's advanced 2.5V specified
PowerTrench process with state of the art BGA
packaging, the FDZ203N minimizes both PCB space
and R
DS(ON)
. This BGA MOSFET embodies a
breakthrough in packaging technology which enables
the device to combine excellent thermal transfer
characteristics, high current handling capability, ultra-
low profile packaging, low gate charge, and low R
DS(ON)
.
Applications
Battery management
Load switch
Battery protection
Features
7.5 A, 20 V.
R
DS(ON)
= 18 m
@ V
GS
= 4.5
R
DS(ON)
= 30 m
@ V
GS
= 2.5 V
Occupies only 4 mm
2
of PCB area.
Less than 40% of the area of a SSOT-6
Ultra-thin package: less than 0.80 mm height when
mounted to PCB
Ultra-low Q
g
x R
DS(ON)
figure-of-merit.
High power and current handling capability.
GATE
Bottom
Index
slot
Top
Absolute Maximum Ratings
T
A
=25
o
C unless otherwise noted
Symbol Parameter
Ratings
Units
V
DSS
Drain-Source Voltage
20
V
V
GSS
Gate-Source
Voltage
12
V
I
D
Drain Current Continuous
(Note 1a)
7.5 A
Pulsed
20
P
D
Power Dissipation (Steady State)
(Note 1a)
1.6 W
T
J
, T
STG
Operating and Storage Junction Temperature Range
55 to +150
C
Thermal Characteristics
R
JA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
67
C/W
R
JB
Thermal Resistance, Junction-to-Ball
(Note 1)
11
R
JC
Thermal Resistance, Junction-to-Case
(Note 1)
1
Package Marking and Ordering Information
Device Marking
Device
Reel Size
Tape width
Quantity
203N
FDZ203N
7''
8mm
3000 units
FDZ203N
S
D
G
FDZ203N Rev.E6(W)
Electrical Characteristics
T
A
= 25C unless otherwise noted
Symbol Parameter
Test
Conditions
Min
Typ
Max
Units
Off Characteristics
BV
DSS
DrainSource Breakdown Voltage V
GS
= 0 V, I
D
= 250
A
20 V
BV
DSS
T
J
Breakdown Voltage Temperature
Coefficient
I
D
= 250
A, Referenced to 25
C
14
mV/
C
I
DSS
Zero Gate Voltage Drain Current
V
DS
= 16 V,
V
GS
= 0 V
1
A
I
GSSF
GateBody Leakage, Forward
V
GS
= 12 V,
V
DS
= 0 V
100
nA
I
GSSR
GateBody Leakage, Reverse
V
GS
= 12 V, V
DS
= 0 V
100
nA
On Characteristics
(Note 2)
V
GS(th)
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= 250
A
0.6 0.8 1.5 V
V
GS(th)
T
J
Gate Threshold Voltage
Temperature Coefficient
I
D
= 250
A, Referenced to 25
C
3
mV/
C
R
DS(on)
Static DrainSource
OnResistance
V
GS
= 4.5 V,
I
D
= 7.5 A
V
GS
= 2.5 V,
I
D
= 5.5 A
V
GS
= 4.5 V, I
D
= 7.5 A, T
J
=125
C
14
20
20
18
30
28
m
I
D(on)
OnState Drain Current
V
GS
= 4.5 V,
V
DS
= 5 V
20
A
g
FS
Forward
Transconductance V
DS
= 10 V,
I
D
= 7.5 A
33
S
Dynamic Characteristics
C
iss
Input
Capacitance
1127
pF
C
oss
Output
Capacitance
268
pF
C
rss
Reverse Transfer Capacitance
V
DS
= 10 V,
V
GS
= 0 V,
f = 1.0 MHz
134 pF
Switching Characteristics
(Note
2)
t
d(on)
TurnOn
Delay
Time
8
16
ns
t
r
TurnOn Rise Time
11
20
ns
t
d(off)
TurnOff Delay Time
26
42
ns
t
f
TurnOff
Fall
Time
V
DD
= 10V,
I
D
= 1 A,
V
GS
= 4.5 V,
R
GEN
= 6
8
16
ns
Q
g
Total Gate Charge
11
15
nC
Q
gs
GateSource
Charge
2
nC
Q
gd
GateDrain
Charge
V
DS
= 10 V,
I
D
= 7.5 A,
V
GS
= 4.5 V
3 nC
DrainSource Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous DrainSource Diode Forward Current
1.3
A
V
SD
DrainSource
Diode
Forward
Voltage
V
GS
= 0 V, I
S
= 1.3 A
(Note 2)
0.7 1.2 V
t
rr
Diode Reverse Recovery Time
20
nS
Q
rr
Diode Reverse Recovery Charge
I
F
= 9A,
d
iF
/d
t
= 100 A/s
14 nC
Notes:
1.
R
JA
is determined with the device mounted on a 1 in 2 oz. copper pad on a 1.5 x 1.5 in. board of FR-4 material. The thermal resistance from the junction to
the circuit board side of the solder ball, R
JB
, is defined for reference. For R
JC
, the thermal reference point for the case is defined as the top surface of the
copper chip carrier. R
JC
and R
JB
are guaranteed by design while R
JA
is determined by the user's board design.
a)
67 C/W when
mounted on a 1in
2
pad
of 2 oz copper, 1.5" x
1.5" x 0.062" thick
PCB
b)
155 C/W when mounted
on a minimum pad of 2 oz
copper
Scale 1 : 1 on letter size paper
2. 2.
Pulse Test: Pulse Width < 300
s, Duty Cycle < 2.0%
FDZ203N
FDZ203N Rev.E6(W)
Dimensional Outline and Pad
Layout
FDZ203N
FDZ203N Rev.E6(W)
Typical Characteristics
0
5
10
15
20
25
30
0
0.5
1
1.5
2
2.5
3
3.5
V
DS
, DRAIN-SOURCE VOLTAGE (V)
I
D
,
DRAI
N CURRENT (
A
)
3.0V
3.5V
2.5V
2.0V
V
GS
= 4.5V
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
0
5
10
15
20
25
30
I
D
, DRAIN CURRENT (A)
R
DS
(
O
N)
, NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
V
GS
= 2.0V
3.5V
3.0V
4.0V
4.5V
2.5V
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
0.6
0.8
1
1.2
1.4
1.6
-50
-25
0
25
50
75
100
125
150
T
J
, JUNCTION TEMPERATURE (
o
C)
R
DS(O
N)
,
NORMALI
Z
ED
DRAI
N-
SOURCE ON-
R
ESI
S
TANCE
I
D
= 9A
V
GS
= 4.5V
0.01
0.02
0.03
0.04
0.05
0.06
0.07
1
2
3
4
5
V
GS
, GATE TO SOURCE VOLTAGE (V)
R
DS(O
N)
, ON-
R
ESIST
ANCE (
O
HM
)
I
D
= 4.5 A
T
A
= 125
o
C
T
A
= 25
o
C
Figure 3. On-Resistance Variation with
Temperature.
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
0
5
10
15
20
25
0.5
1
1.5
2
2.5
V
GS
, GATE TO SOURCE VOLTAGE (V)
I
D
, DRAIN CURRE
NT
(A)
T
A
= -55
o
C
25
o
C
125
o
C
V
DS
= 5V
0.0001
0.001
0.01
0.1
1
10
100
0
0.2
0.4
0.6
0.8
1
1.2
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
I
S
, REVERSE DRAIN CURRENT (A)
T
A
= 125
o
C
25
o
C
-55
o
C
V
GS
= 0V
Figure 5. Transfer Characteristics.
Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature.
FDZ203N
FDZ203N Rev.E6(W)
Typical Characteristics
0
1
2
3
4
5
0
2
4
6
8
10
12
14
Q
g
, GATE CHARGE (nC)
V
GS
,
GATE-
S
OURCE VOLTAGE (
V
)
I
D
= 9A
V
DS
= 5V
15V
10V
0
300
600
900
1200
1500
1800
0
5
10
15
20
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (
pF)
C
ISS
C
RSS
C
OSS
f = 1MHz
V
GS
= 0 V
Figure 7. Gate Charge Characteristics.
Figure 8. Capacitance Characteristics.
0.01
0.1
1
10
100
0.1
1
10
100
V
DS
, DRAIN-SOURCE VOLTAGE (V)
I
D
, DRAIN CURRENT (A)
DC
10s
1s
100ms
R
DS(ON)
LIMIT
V
GS
= 4.5V
SINGLE PULSE
R
JA
= 155
o
C/W
T
A
= 25
o
C
10ms
1ms
0
10
20
30
40
50
0.01
0.1
1
10
100
1000
t
1
, TIME (sec)
P(pk), PEAK TRANSIENT POWER (W)
SINGLE PULSE
R
JA
= 155C/W
T
A
= 25C
Figure 9. Maximum Safe Operating Area.
Figure 10. Single Pulse Maximum
Power Dissipation.
0.001
0.01
0.1
1
0.001
0.01
0.1
1
10
100
1000
t
1
, TIME (sec)
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
R
JA
(t) = r(t) + R
JA
R
JA
= 155 C/W
T
J
- T
A
= P * R
JA
(t)
Duty Cycle, D = t
1
/ t
2
P(pk)
t
1
t
2
SINGLE PULSE
0.01
0.02
0.05
0.1
0.2
D = 0.5
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1b.
Transient thermal response will change depending on the circuit board design.


FDZ203N