2000 Fairchild Semiconductor Corporation
DS006388
www.fairchildsemi.com
August 1986
Revised March 2000
DM74LS126
A
Quad 3
-
ST
A
T
E Buf
f
er
DM74LS126A
Quad 3-STATE Buffer
General Description
This device contains four independent gates each of which
performs a non-inverting buffer function. The outputs have
the 3-STATE feature. When enabled, the outputs exhibit
the low impedance characteristics of a standard LS output
with additional drive capability to permit the driving of bus
lines without external resistors. When disabled, both the
output transistors are turned OFF presenting a high-imped-
ance state to the bus line. Thus the output will act neither
as a significant load nor as a driver. To minimize the possi-
bility that two outputs will attempt to take a common bus to
opposite logic levels, the disable time is shorter than the
enable time of the outputs.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Function Table
Y
=
A
H
=
HIGH Logic Level
L
=
LOW Logic Level
X
=
Either LOW or HIGH Logic Level
Hi-Z
=
3-STATE (Outputs are disabled)
Order Number
Package Number
Package Description
DM74LS126AM
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS126AN
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs
Output
A
C
Y
L
H
L
H
H
H
X
L
Hi-Z
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2
D
M
74LS12
6A
Absolute Maximum Ratings
(Note 1)
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Recommended Operating Conditions
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Note 2: All typicals are at V
CC
=
5V, T
A
=
25
C.
Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Switching Characteristics
V
CC
=
5V, T
A
=
25
C
Note 4: C
L
=
5pF.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
0
C to
+
70
C
Storage Temperature Range
-
65
C to
+
150
C
Symbol
Parameter
Min
Nom
Max
Units
V
CC
Supply Voltage
4.75
5
5.25
V
V
IH
HIGH Level Input Voltage
V
V
IL
LOW Level Input Voltage
0.8
V
I
OH
HIGH Level Output Current
-
2.6
mA
I
OL
LOW Level Output Current
24
mA
T
A
Free Air Operating Temperature
0
70
C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 2)
V
I
Input Clamp Voltage
V
CC
=
Min, I
I
=
-
18 mA
-
1.5
V
V
OH
HIGH Level
V
CC
=
Min, I
OH
=
Max
2.4
V
Output Voltage
V
IH
=
Min
V
OL
LOW
Level V
CC
=
Min, I
OL
=
Max
0.35
0.5
Output Voltage
V
IL
=
Max, V
IH
=
Min
V
I
OL
=
12 mA, V
CC
=
Min
0.25
0.4
I
I
Input Current @ Max Input Voltage
V
CC
=
Max, V
I
=
7V
0.1
mA
I
IH
HIGH Level Input Current
V
CC
=
Max, V
I
=
2.7V
20
A
I
IL
LOW Level Input Current
V
CC
=
Max, V
I
=
0.4V
-
0.4
mA
I
OZH
Off-State Output Current with
V
CC
=
Max, V
O
=
2.4V
20
A
HIGH Level Output Voltage Applied
V
IH
=
Min, V
IL
=
Max
I
OZL
Off-State Output Current with
V
CC
=
Max, V
O
=
0.4V
-
20
A
LOW Level Output Voltage Applied
V
IH
=
Min, V
IL
=
Max
I
OS
Short Circuit Output Current
V
CC
=
Max (Note 3)
-
20
-
100
mA
I
CC
Supply Current
V
CC
=
Max
12
22
mA
R
L
=
667
Symbol
Parameter
C
L
=
50 pF
C
L
=
150 pF
Units
Min
Max
Min
Max
t
PLH
Propagation Delay Time LOW-to-HIGH Level Output
15
21
ns
t
PHL
Propagation Delay Time HIGH-to-LOW Level Output
18
22
ns
t
PZH
Output Enable Time to HIGH Level Output
30
36
ns
t
PZL
Output Enable Time to LOW Level Output
30
42
ns
t
PHZ
Output Disable Time from HIGH Level Output (Note 4)
25
ns
t
PLZ
Output Disable Time from LOW Level Output (Note 4)
25
ns
3
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DM74LS126
A
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
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4
DM74LS126
A
Quad 3-ST
A
T
E
Buf
f
er
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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