1999 Fairchild Semiconductor Corporation
DS011667
www.fairchildsemi.com
March 1994
Revised November 1999
7
4
AB
T1
25
Quad Buff
er wit
h
3-
ST
A
T
E Output
s
74ABT125
Quad Buffer with 3-STATE Outputs
General Description
The ABT125 contains four independent non-inverting buff-
ers with 3-STATE outputs.
Features
s
Non-inverting buffers
s
Output sink capability of 64 mA, source capability of
32 mA
s
Guaranteed latchup protection
s
High impedance glitch free bus loading during entire
power up and power down cycle
s
Nondestructive hot insertion capability
s
Disable time less than enable time to avoid bus conten-
tion
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Pin Descriptions
Function Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
Z
=
HIGH Impedance
X
=
Immaterial
Order Number
Package Number
Package Description
74ABT125CSC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow Body
74ABT125CSJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT125CMTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,4.4mm Wide
Pin Names
Descriptions
A
n
, B
n
Inputs
O
n
Outputs
Inputs
Output
A
n
B
n
O
n
L
L
L
L
H
H
H
X
Z
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2
74ABT125
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Note 3: Guaranteed, but not tested.
Note 4: For 8 bits toggling, I
CCD
<
0.8 mA/MHz.
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
55
C to
+
125
C
Junction Temperature under Bias
-
55
C to
+
150
C
V
CC
Pin Potential to
Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 2)
-
0.5V to
+
7.0V
Input Current (Note 2)
-
30 mA to
+
5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-Off State
-
0.5V to 5.5V
in the HIGH State
-
0.5V to V
CC
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
DC Latchup Source Current
(Across Comm Operating Range)
-
300 mA
Over Voltage Latchup (I/O)
10V
Free Air Ambient Temperature
-
40
C to
+
85
C
Supply Voltage
+
4.5V to
+
5.5V
Minimum Input Edge Rate (
V/
t)
Data Input
50 mV/ns
Enable Input
20 mV/ns
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
V
Recognized HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
Min
I
IN
=
-
18 mA
V
OH
Output HIGH Voltage
2.5
V
Min
I
OH
=
-
3 mA
2.0
V
Min
I
OH
=
-
32 mA
V
OL
Output LOW Voltage
0.55
V
Min
I
OL
=
64 mA
I
IH
Input HIGH Current
1
A
Max
V
IN
=
2.7V (Note 3)
1
V
IN
=
V
CC
I
BVI
Input HIGH Current Breakdown Test
7
A
Max
V
IN
=
7.0V
I
IL
Input LOW Current
-
1
A
Max
V
IN
=
0.5V (Note 3)
-
1
V
IN
=
0.0V
V
ID
Input Leakage Test
V
0.0
I
ID
=
1.9
A, All Other Pin Grounded
I
OZH
Output Leakage Current
10
A
0
-
5.5V
V
OUT
=
2.7V; OE
n
=
2.0V
I
OZL
Output Leakage Current
-
10
A
0
-
5.5V
V
OUT
=
0.5V; OE
n
=
2.0V
I
OS
Output Short-Circuit Current
-
275
mA
Max
V
OUT
=
0.0V
I
CEX
Output HIGH Leakage Current
50
A
Max
V
OUT
=
V
CC
I
ZZ
Bus Drainage Test
100
A
0.0
V
OUT
=
5.5V; All Others GND
I
CCH
Power Supply Current
50
A
Max
All Outputs HIGH
I
CCL
Power Supply Current
15
mA
Max
All Outputs LOW
I
CCZ
Power Supply Current
50
A
Max
OE
n
=
V
CC
;
All Others at V
CC
or Ground
I
CCT
Additional I
CC
/Input
Outputs Enabled
1.5
mA
Max
V
I
=
V
CC
-
2.1V
Outputs 3-STATE
1.5
mA
Enable Input V
I
=
V
CC
-
2.1V
Outputs 3-STATE
50
A
Data Input V
I
=
V
CC
-
2.1V
All Others at V
CC
or Ground
I
CCD
Dynamic I
CC
No Load
mA/
Max
Outputs Open
(Note 3)
0.1
MHz
OE
n
=
GND, (Note 4)
One Bit Toggling, 50% Duty Cycle
3
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74
A
B
T
1
2
5
AC Electrical Characteristics
Capacitance
Note 5: C
OUT
is measured at frequency f
=
1 MHz, per MIL-STD-883, Method 3012.
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Symbol
Parameter
V
CC
=
+
5V
V
CC
=
4.5V5.5V
Units
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay
1.0
4.6
1.0
4.6
ns
t
PHL
Data to Outputs
1.0
4.9
1.0
4.9
t
PZH
Output Enable
1.0
5.1
1.0
5.1
ns
t
PZL
Time
1.0
6.8
1.0
6.8
t
PHZ
Output Disable
1.0
6.2
1.0
6.2
ns
t
PLZ
Time
1.0
5.5
1.0
5.5
Symbol
Parameter
Typ
Units
Conditions
T
A
=
25
C
C
IN
Input Capacitance
5.0
pF
V
CC
=
0V
C
OUT
(Note 5)
Output Capacitance
9.0
pF
V
CC
=
5.0V
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4
74ABT125
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body
Package Number M14A
5
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74
A
B
T
1
2
5
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
www.fairchildsemi.com
6
74ABT125 Quad
Buf
f
e
r
wi
th 3-
S
T
A
T
E O
u
t
puts
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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