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Электронный компонент: 74ABT162244CMTD

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2005 Fairchild Semiconductor Corporation
DS010987
www.fairchildsemi.com
April 1992
Revised May 2005
7
4
AB
T1
62244
16-Bi
t
Buff
er/
L
ine
Dri
ver
wit
h
2
5
:
Seri
es Resist
ors in

t
he
Out
put
s
74ABT162244
16-Bit Buffer/Line Driver with
25
:
Series Resistors in the Outputs
General Description
The ABT162244 contains sixteen non-inverting buffers with
3-STATE outputs designed to be employed as a memory
and address driver, clock driver, or bus oriented transmit-
ter/receiver. The device is nibble controlled. Individual
3-STATE control inputs can be shorted together for 8-bit or
16-bit operation.
The 25
:
series resistors in the outputs reduce ringing and
eliminate the need for external resistors.
Features
s
Separate control logic for each nibble
s
16-bit version of the ABT2244
s
Guaranteed latchup protection
s
High impedance glitch free bus loading during entire
power up and power down cycle
s
Non-destructive hot insertion capability
Ordering Code:
Logic Symbol
Pin Descriptions
Connection Diagram
Order Number
Package Number
Package Description
74ABT162244CSSC
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[RAIL]
74ABT162244CSSX
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TAPE and REEL]
74ABT162244CMTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[RAIL]
74ABT162244MTDX
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Pin Names
Description
OE
n
Output Enable Input (Active LOW)
I
0
I
15
Inputs
O
0
O
15
Outputs
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2
74ABT162244
Truth Tables
H
HIGH Voltage Level
L
LOW Voltage Level
X
Immaterial
Z
High Impedance
Functional Description
The ABT162244 contains sixteen non-inverting buffers with
3-STATE outputs. The device is nibble (4 bits) controlled
with each nibble functioning identically, but independent of
the other. The control pins can be shorted together to
obtain full 16-bit operation.
Logic Diagram
Schematic of each Output
Inputs
Outputs
OE
1
I
0
I
3
O
0
O
3
L
L
L
L
H
H
H
X
Z
Inputs
Outputs
OE
3
I
8
I
11
O
8
O
11
L
L
L
L
H
H
H
X
Z
Inputs
Outputs
OE
2
I
4
I
7
O
4
O
7
L
L
L
L
H
H
H
X
Z
Inputs
Outputs
OE
4
I
12
I
15
O
12
O
15
L
L
L
L
H
H
H
X
Z
3
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62244
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Note 3: Guaranteed, but not tested.
Storage Temperature
65
q
C to
150
q
C
Ambient Temperature under Bias
55
q
C to
125
q
C
Junction Temperature under Bias
55
q
C to
150
q
C
V
CC
Pin Potential to Ground Pin
0.5V to
7.0V
Input Voltage (Note 2)
0.5V to
7.0V
Input Current (Note 2)
30 mA to
5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-Off State
0.5V to 5.5V
in the HIGH State
0.5V to V
CC
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
DC Latchup Source Current
500 mA
Over Voltage Latchup (I/O)
10V
Free Air Ambient Temperature
40
q
C to
85
q
C
Supply Voltage
4.5V to
5.5V
Minimum Input Edge Rate (
'
V/
'
t)
Data Input
50 mV/ns
Enable Input
20 mV/ns
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized LOW Signal
V
CD
Input Clamp Diode Voltage
1.2
V
Min
I
IN
18 mA
V
OH
Output HIGH Voltage
2.5
V
Min
I
OH
3 mA
2.0
V
Min
I
OH
32 mA
V
OL
Output LOW Voltage
0.8
V
Min
I
OL
12 mA
I
IH
Input HIGH Current
1
P
A
Max
V
IN
2.7V (Note 3)
1
V
IN
V
CC
I
BVI
Input HIGH Current Breakdown Test
7
P
A
Max
V
IN
7.0V
I
IL
Input LOW Current
1
P
A
Max
V
IN
0.5V (Note 3)
1
V
IN
0.0V
V
ID
Input Leakage Test
4.75
V
0.0
I
ID
1.9
P
A
All Other Pins Grounded
I
OZH
Output Leakage Current
10
P
A
0
5.5V
V
OUT
2.7V; OE
n
2.0V
I
OZL
Output Leakage Current
10
P
A
0
5.5V
V
OUT
0.5V; OE
n
2.0V
I
OS
Output Short-Circuit Current
100
275
mA
Max
V
OUT
0.0V
I
CEX
Output High Leakage Current
50
P
A
Max
V
OUT
V
CC
I
ZZ
Bus Drainage Test
100
P
A
0.0
V
OUT
5.5V; All Others GND
I
CCH
Power Supply Current
2.0
mA
Max
All Outputs HIGH
I
CCL
Power Supply Current
60
mA
Max
All Outputs LOW
I
CCZ
Power Supply Current
2.0
mA
Max
OE
n
V
CC
All Others at V
CC
or GND
I
CCT
Additional I
CC
/Input
Outputs Enabled
3.0
mA
V
I
V
CC
2.1V
Outputs 3-STATE
3.0
mA
Max
Enable Input V
I
V
CC
2.1V
Outputs 3-STATE
50
P
A
Data Input V
I
V
CC
2.1V
All Others at V
CC
or GND
I
CCD
Dynamic I
CC
No Load
mA/
Max
Outputs OPEN
(Note 3)
0.1
MHz
OE
n
GND
One Bit Toggling, 50% Duty Cycle
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4
74ABT162244
AC Electrical Characteristics
Capacitance
Note 4: C
OUT
is measured at frequency f
1 MHz per MIL-STD-883, Method 3012.
Symbol
Parameter
T
A
25
q
C
T
A
40
q
C to
85
q
C
Units
V
CC
5V
V
CC
4.5V5.5V
C
L
50 pF
C
L
50 pF
Min
Typ
Max
Min
Max
t
PLH
Propagation
1.0
2.4
3.9
1.0
3.9
ns
t
PHL
Delay Data to Outputs
1.0
3.2
4.7
1.0
4.7
t
PZH
Output
1.5
3.5
6.3
1.5
6.3
ns
t
PZL
Enable Time
1.5
4.2
6.9
1.5
6.9
t
PHZ
Output
1.0
4.2
6.7
1.0
6.7
ns
t
PLZ
Disable Time
1.0
3.8
6.7
1.0
6.7
Symbol
Parameter
Typ
Units
Conditions
T
A
25
q
C
C
IN
Input Capacitance
5.0
pF
V
CC
0.0V
C
OUT
(Note 4)
Output Capacitance
9.0
pF
V
CC
5.0V
5
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AC Loading
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
FIGURE 2. Input Pulse Requirements
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 4. Propagation Delay Waveforms for Inverting
and Non-Inverting Functions
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
FIGURE 6. 3-STATE Output HIGH
and LOW Enable and Disable Times
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
Amplitude
Rep. Rate
t
W
t
r
t
f
3.0V
1 MHz
500 ns
2.5 ns
2.5 ns