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Электронный компонент: 74ABT16244

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2005 Fairchild Semiconductor Corporation
DS010985
www.fairchildsemi.com
April 1992
Revised May 2005
7
4
AB
T1
6244
1
6
-Bi
t
Buff
er/
L
ine Dri
ver wit
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3-
ST
A
T
E Output
s
74ABT16244
16-Bit Buffer/Line Driver with 3-STATE Outputs
General Description
The ABT16244 contains sixteen non-inverting buffers with
3-STATE outputs designed to be employed as a memory
and address driver, clock driver, or bus oriented transmit-
ter/receiver. The device is nibble controlled. Individual 3-
STATE control inputs can be shorted together for 8-bit or
16-bit operation.
Features
s
Separate control logic for each nibble
s
16-bit version of the ABT244
s
Outputs sink capability of 64 mA, source capability of
32 mA
s
Guaranteed output skew
s
Guaranteed multiple output switching specifications
s
Output switching specified for both 50 pF and
250 pF loads
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed latchup protection
s
High impedance glitch free bus loading during entire
power up and power down cycle
s
Non-destructive hot insertion capability
Ordering Code:
Devices are also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagram
Order Number
Package Number
Package Description
74ABT16244CSSC
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74ABT16244CMTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names
Description
OE
n
Output Enable Inputs (Active LOW)
I
0
I
15
Inputs
O
0
O
15
Outputs
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2
74ABT16244
Truth Tables
H
HIGH Voltage Level
L
LOW Voltage Level
X
Immaterial
Z
High Impedance
Functional Description
The ABT16244 contains sixteen non-inverting buffers with
3-STATE outputs. The device is nibble (4 bits) controlled
with each nibble functioning identically, but independent of
the other. The control pins can be shorted together to
obtain full 16-bit operation.
Logic Diagram
Inputs
Outputs
OE
1
I
0
I
3
O
0
O
3
L
L
L
L
H
H
H
X
Z
Inputs
Outputs
OE
2
I
4
I
7
O
4
O
7
L
L
L
L
H
H
H
X
Z
Inputs
Outputs
OE
3
I
8
I
11
O
8
O
11
L
L
L
L
H
H
H
X
Z
Inputs
Outputs
OE
4
I
12
I
15
O
12
O
15
L
L
L
L
H
H
H
X
Z
3
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AB
T1
6244
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Note 3: Guaranteed but not tested.
Storage Temperature
65
q
C to
150
q
C
Ambient Temperature under Bias
55
q
C to
125
q
C
Junction Temperature under Bias
55
q
C to
150
q
C
V
CC
Pin Potential to Ground Pin
0.5V to
7.0V
Input Voltage (Note 2)
0.5V to
7.0V
Input Current (Note 2)
30 mA to
5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-Off
State
0.5V to 5.5V
in the HIGH State
0.5V to V
CC
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
DC Latchup Source Current
500 mA
Over Voltage Latchup (I/O)
10V
Free Air Ambient Temperature
40
q
C to
85
q
C
Supply Voltage
4.5V to
5.5V
Minimum Input Edge Rate (
'
V/
'
t)
Data Input
50 mV/ns
Enable Input
20 mV/ns
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized LOW Signal
V
CD
Input Clamp Diode Voltage
1.2
V
Min
I
IN
18 mA
V
OH
Output HIGH Voltage
2.5
V
Min
I
OH
3 mA
2.0
V
Min
I
OH
32 mA
V
OL
Output LOW Voltage
0.55
V
Min
I
OL
64 mA
I
IH
Input HIGH Current
1
P
A
Max
V
IN
2.7V (Note 3)
1
V
IN
V
CC
I
BVI
Input HIGH Current
7
P
A
Max
V
IN
7.0V
Breakdown Test
I
IL
Input LOW Current
1
P
A
Max
V
IN
0.5V (Note 3)
1
V
IN
0.0V
V
ID
Input Leakage Test
4.75
V
0.0
I
ID
1.9
P
A
All Other Pins Grounded
I
OZH
Output Leakage Current
10
P
A
0
5.5V V
OUT
2.7V; OE
n
2.0V
I
OZL
Output Leakage Current
10
P
A
0
5.5V V
OUT
0.5V; OE
n
2.0V
I
OS
Output Short-Circuit Current
100
275
mA
Max
V
OUT
0.0V
I
CEX
Output HIGH Leakage Current
50
P
A
Max
V
OUT
V
CC
I
ZZ
Bus Drainage Test
100
P
A
0.0
V
OUT
5.5V
All Other Pins GND
I
CCH
Power Supply Current
2.0
mA
Max
All Outputs HIGH
I
CCL
Power Supply Current
60
mA
Max
All Outputs LOW
I
CCZ
Power Supply Current
2.0
mA
Max
OE
n
V
CC
All Others at V
CC
or GND
I
CCT
Additional I
CC
/Input
Outputs Enabled
2.5
mA
V
I
V
CC
2.1V
Outputs 3-STATE
2.5
mA
Max
Enable Input V
I
V
CC
2.1V
Outputs 3-STATE
50
P
A
Data Input V
I
V
CC
2.1V
All Others at V
CC
or GND
I
CCD
Dynamic I
CC
No Load
mA/
Max
Outputs Open, OE
n
GND
(Note 3)
0.1
MHz
One Bit Toggling,
50% Duty Cycle
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74ABT16244
DC Electrical Characteristics
Note 4: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 5: Max number of outputs defined as (n). n
1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
Note 6: Max number of data inputs (n) switching. n-1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V
ILD
), 0V to threshold (V
IHD
).
Guaranteed, but not tested.
AC Electrical Characteristics
Extended AC Electrical Characteristics
Note 7: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 8: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 9: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 10: The 3-STATE delay times are dominated by the RC network (500
:
, 250 pF) on the output and have been excluded from the datasheet.
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
C
L
50 pF, R
L
500
:
V
OLP
Quiet Output Maximum Dynamic V
OL
0.4
0.7
V
5.0
T
A
25
q
C (Note 4)
V
OLV
Quiet Output Minimum Dynamic V
OL
1.3
1.0
V
5.0
T
A
25
q
C (Note 4)
V
OHV
Minimum HIGH Level Dynamic Output Voltage
2.7
3.0
V
5.0
T
A
25
q
C (Note 5)
V
IHD
Minimum HIGH Level Dynamic Input Voltage
2.0
1.4
V
5.0
T
A
25
q
C (Note 6)
V
ILD
Maximum LOW Level Dynamic Input Voltage
1.2
0.8
V
5.0
T
A
25
q
C (Note 6)
Symbol
Parameter
T
A
25
q
C
T
A
40
q
C to
85
q
C
Units
V
CC
5V
V
CC
4.5V5.5V
C
L
50 pF
C
L
50 pF
Min
Typ
Max
Min
Max
t
PLH
Propagation
1.0
2.3
3.9
1.0
3.9
ns
t
PHL
Delay Data to Outputs
1.0
2.7
3.9
1.0
3.9
t
PZH
Output Enable
1.5
3.5
6.3
1.5
6.3
ns
t
PZL
Time
1.5
3.5
6.3
1.5
6.3
t
PHZ
Output Disable
1.0
4.2
6.7
1.0
6.7
ns
t
PLZ
Time
1.0
3.2
6.7
1.0
6.7
Symbol
Parameter
40
q
C to
85
q
C
T
A
40
q
C to
85
q
C
T
A
40
q
C to
85
q
C
Units
V
CC
4.5V5.5V
V
CC
4.5V5.5V
V
CC
4.5V5.5V
C
L
50 pF
C
L
250 pF
C
L
250 pF
16 Outputs Switching
1 Output Switching
16 Outputs Switching
(Note 7)
(Note 8)
(Note 9)
Min
Typ
Max
Min
Max
Min
Max
f
TOGGLE
Max Toggle Frequency
100
MHz
t
PLH
Propagation Delay
1.5
5.0
1.5
6.0
2.5
8.0
ns
t
PHL
Data to Outputs
1.5
5.3
1.5
6.0
2.5
8.0
t
PZH
Output Enable Time
1.5
6.5
2.5
7.8
2.5
9.5
ns
t
PZL
1.5
6.5
2.5
7.8
2.5
8.5
t
PHZ
Output Disable Time
1.0
6.7
(Note 10)
(Note 10)
ns
t
PLZ
1.0
6.7
5
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AB
T1
6244
Skew
Note 11: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.)
Note 12: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 13: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH to LOW (t
OSHL
), LOW-to-HIGH (t
OSLH
), or any combination switching LOW-to-HIGH and/or HIGH-to-
LOW (t
OST
). The specification is guaranteed but not tested.
Note 14: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Note 15: Propagation delay variation for a given set of conditions (i.e., temperature and V
CC
) from device to device. This specification is guaranteed but not
tested.
Capacitance
Note 16: C
OUT
is measured at frequency f
1 MHz; per MIL STD-883, Method 3012.
Symbol
Parameter
T
A
40
q
C to
85
q
C
T
A
40
q
C to
85
q
C
Units
V
CC
4.5V5.5V
V
CC
4.5V5.5V
C
L
50 pF
C
L
250 pF
16 Outputs Switching
16 Outputs Switching
(Note 11)
(Note 12)
Max
Max
t
OSHL
Pin to Pin Skew
1.0
1.5
ns
(Note 13)
HL Transitions
t
OSLH
Pin to Pin Skew
1.0
1.5
ns
(Note 13)
LH Transitions
t
PS
Duty Cycle
1.5
1.5
ns
(Note 14)
LHHL Skew
t
OST
Pin to Pin Skew
1.7
2.0
ns
(Note 13)
LH/HL Transitions
t
PV
Device to Device Skew
2.0
2.5
ns
(Note 15)
LH/HL Transitions
Symbol
Parameter
Typ
Units
Conditions
T
A
25
q
C
C
IN
Input Capacitance
5.0
pF
V
CC
5.0V
C
OUT
(Note 16)
Output Capacitance
9.0
pF
V
CC
5.0V