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Электронный компонент: 74ABT16500

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April 1993
Revised January 1999
7
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AB
T1
6500 1
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1999 Fairchild Semiconductor Corporation
DS011581.prf
www.fairchildsemi.com
74ABT16500
18-Bit Universal Bus Transceivers with 3-STATE Outputs
General Description
The ABT16500 18-bit universal bus transceiver combines
D-type latches and D-type flip-flops to allow data flow in
transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in the transparent mode when LEAB is
HIGH. When LEAB is LOW, the A data is latched if CLKAB
is held at a HIGH or LOW logic level. If LEAB is LOW, the A
bus data is stored in the latch/flip-flop on the HIGH-to-LOW
transition of CLKAB. Output-enable OEAB is active-high.
When OEAB is HIGH, the outputs are active. When OEAB
is LOW, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA, LEBA, and CLKBA. The output enables are com-
plementary (OEAB is active HIGH and OEBA is active
LOW).
To ensure the high-impedance state during power up or
power down, OE should be tied to GND through a pulldown
resistor; the minimum value of the resistor is determined by
the current-sourcing capability of the driver.
Features
s
Combines D-Type latches and D-Type flip-flops for
operation in transparent, latched, or clocked mode
s
Flow-through architecture optimizes PCB layout
s
Guaranteed latch-up protection
s
High impedance glitch free bus loading during entire
power up and power down cycle
s
Non-destructive hot insertion capability
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the letter suffix "X" to the ordering code.
Connection Diagram
Pin Assignment for SSOP
Function Table
(Note 1)
Note 1: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,
LEBA, and CLKBA.
Note 2: Output level before the indicated steady-state input conditions
were established.
Note 3: Output level before the indicated steady-state input conditions
were established, provided that CLKAB was LOW before LEAB went LOW.
Order Number
Package Number
Package Description
74ABT16500CSSC MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74ABT16500CMTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Inputs
Output
OEAB
LEAB
CLKAB
A
B
L
X
X
X
Z
H
H
X
L
L
H
H
X
H
H
H
L
L
L
H
L
H
H
H
L
H
X
B
0
(Note 2)
H
L
L
X
B
0
(Note 3)
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2
74ABT16500
Logic Diagram
3
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AB
T1
6500
Absolute Maximum Ratings
(Note 4)
Recommended Operating
Conditions
Note 4: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 5: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Note 6: Guaranteed, but not tested.
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
55
C to
+
125
C
Junction Temperature under Bias
-
55
C to
+
150
C
V
CC
Pin Potential to
Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 5)
-
0.5V to
+
7.0V
Input Current (Note 5)
-
30 mA to
+
5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-off State
-
0.5V to 5.5V
in the HIGH State
-
0.5V to V
CC
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
DC Latchup Source Current
-
500 mA
Over Voltage Latchup (I/O)
10V
Free Air Ambient Temperature
-
40
C to
+
85
C
Supply Voltage
+
4.5V to
+
5.5V
Minimum Input Edge Rate (
V/
t)
Data Input
50 mV/ns
Enable Input
20 mV/ns
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
Min
I
IN
=
-
18 mA
V
OH
Output HIGH Voltage
2.5
V
Min
I
OH
=
-
3 mA
2.0
V
Min
I
OH
=
-
32 mA
V
OL
Output LOW Voltage
0.55
V
Min
I
OL
=
64 mA
I
IH
Input HIGH Current
1
A
Max
V
IN
=
2.7V (Note 6)
1
V
IN
=
V
CC
I
BVI
Input HIGH Current Breakdown Test
7
A
Max
V
IN
=
7.0V
I
IL
Input LOW Current
-
1
A
Max
V
IN
=
0.5V (Note 6)
-
1
V
IN
=
0.0V
V
ID
Input Leakage Test
4.75
V
0.0
I
ID
=
1.9
A
All Other Pins Grounded
I
IH
+
Output Leakage Current
10
A
0
-
5.5V
V
OUT
=
2.7V; OE, OE
=
2.0V
I
OZH
I
IL
+
Output Leakage Current
-
10
A
0
-
5.5V
V
OUT
=
0.5V; OE, OE
=
2.0V
I
OZL
I
OS
Output Short-Circuit Current
-
100
-
275
mA
Max
V
OUT
=
0V
I
CEX
Output HIGH Leakage Current
50
A
Max
V
OUT
=
V
CC
I
ZZ
Bus Drainage Test
100
A
0.0
V
OUT
=
5.5V; All Others GND
I
CCH
Power Supply Current
1.0
mA
Max
All Outputs HIGH
I
CCL
Power Supply Current
68
A
Max
An or Bn Outputs Low
I
CCZ
Power Supply Current
1.0
mA
Max
OE
n
=
V
CC
,
All Others at V
CC
or GND
I
CCT
Additional I
CC
/Input
2.5
mA
Max
V
I
=
V
CC
-
2.1V
All Others at V
CC
or GND
I
CCD
Dynamic I
CC
No Load
mA/
Max
Outputs Open
(Note 6)
0.23
MHz
Transparent Mode
One Bit Toggling, 50% Duty Cycle
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74ABT16500
DC Electrical Characteristics
Note 7: Max number of outputs defined as (n). n
-
1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 8: Max number of outputs defined as (n). n
-
1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
Note 9: Max number of data inputs (n) switching. n
-
1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V
ILD
), 0V to threshold (V
IHD
).
Guaranteed, but not tested.
AC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
C
L
=
50 pF; R
L
=
500
V
OLP
Quiet Output Maximum Dynamic V
OL
0.7
1.2
V
5.0
T
A
=
25
C (Note 7)
V
OLV
Quiet Output Minimum Dynamic V
OL
-
1.5
-
1.0
V
5.0
T
A
=
25
C (Note 7)
V
OHV
Minimum HIGH Level Dynamic Output Voltage
2.5
3.0
V
5.0
T
A
=
25
C (Note 8)
V
IHD
Minimum HIGH Level Dynamic Input Voltage
2.2
1.8
V
5.0
T
A
=
25
C (Note 9)
V
ILD
Maximum LOW Level Dynamic Input Voltage
1.2
0.8
V
5.0
T
A
=
25
C (Note 9)
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Units
V
CC
=
+
5V
V
CC
=
4.5V5.5V
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
f
max
Maximum Clock Frequency
150
200
150
MHz
t
PLH
Propagation Delay
1.5
2.7
4.6
1.5
4.6
ns
t
PHL
A or B to B or A
1.5
3.2
4.6
1.5
4.6
t
PLH
Propagation Delay
1.5
3.1
5.0
1.5
5.0
ns
t
PHL
LEAB or LEBA to B or A
1.5
3.6
5.0
1.5
5.0
t
PLH
Propagation Delay
1.5
3.4
5.3
1.5
5.3
ns
t
PHL
CLKAB or CLKBA to B or A
1.5
3.7
5.3
1.5
5.3
t
PZH
Propagation Delay
1.5
2.7
5.6
1.5
5.6
ns
t
PZL
OEAB or OEBA to B or A
1.5
3.0
5.6
1.5
5.6
t
PHZ
Propagation Delay
1.5
3.7
6.0
1.5
6.0
ns
t
PLZ
OEAB or OEBA to B or A
1.5
3.2
6.0
1.5
6.0
5
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AB
T1
6500
AC Operating Requirements
Extended AC Electrical Characteristics
Note 10: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 11: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac-
itors in the standard AC load. This specification pertains to single output switching only.
Note 12: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 13: 3-STATE delays are dominated by the RC network (500
, 250 pF) on the output and have been excluded from the datasheet.
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Units
V
CC
=
+
5V
V
CC
=
4.5V5.5V
C
L
=
50 pF
C
L
=
50 pF
Min
Max
Min
Max
t
S
(H)
Setup Time,
4.5
4.5
ns
t
S
(L)
A to CLKAB
4.5
4.5
t
H
(H)
Hold Time,
0
0
ns
t
H
(L)
A to CLKAB
0
0
t
S
(H)
Setup Time,
4.0
4.0
ns
t
S
(L)
B to CLKBA
4.0
4.0
t
H
(H)
Hold Time,
0
0
ns
t
H
(L)
B to CLKBA
0
0
t
S
(H)
Setup Time, A to LEAB
1.5
1.5
ns
t
S
(L)
or B to LEBA, CLK HIGH
1.5
1.5
t
H
(H)
Hold Time, A to LEAB
1.5
1.5
ns
t
H
(L)
or B to LEBA, CLK HIGH
1.5
1.5
t
S
(H)
Setup Time, A to LEAB
4.5
4.5
ns
t
S
(L)
or B to LEBA, CLK LOW
4.5
4.5
t
H
(H)
Hold Time, A to LEAB
1.5
1.5
ns
t
H
(L)
or B to LEBA, CLK LOW
1.5
1.5
t
W
(H)
Pulse Width,
3.3
3.3
ns
t
W
(L)
LEAB or LEBA, HIGH
3.3
3.3
t
W
(H)
Pulse Width, CLKAB
3.3
3.3
ns
t
W
(L)
or CLKBA, HIGH or LOW
3.3
3.3
Symbol
Parameter
T
A
=
-
40
C to
+
85
C
T
A
=
-
40
C to
+
85
C
T
A
=
-
40
C to
+
85
C
Units
V
CC
=
4.5V5.5V
V
CC
=
4.5V5.5V
V
CC
=
4.5V5.5V
C
L
=
50 pF
C
L
=
250 pF
C
L
=
250 pF
18 Outputs Switching
1 Output Switching
18 Outputs Switching
(Note 10)
(Note 11)
(Note 12)
Min
Typ
Max
Min
Max
Min
Max
t
PLH
Propagation Delay
1.5
6.5
2.0
7.0
2.5
9.9
ns
t
PHL
Data to Outputs
1.5
6.5
2.0
7.0
2.5
9.2
t
PLH
Propagation Delay
1.5
6.0
2.0
7.5
2.5
8.5
ns
t
PHL
LEAB or LEBA to B or A
1.5
6.0
2.0
7.5
2.5
8.5
t
PLH
Propagation Delay
1.5
6.2
2.0
7.7
2.5
8.5
ns
t
PHL
CLKAB or CLKBA to B or A
1.5
6.2
2.0
7.7
2.5
8.5
t
PZH
Output Enable Time
1.5
6.5
2.0
7.0
2.5
8.5
ns
t
PZL
1.5
6.5
2.5
7.0
2.5
8.5
t
PHZ
Output Disable
1.5
6.5
(Note 13)
(Note 13)
ns
t
PLZ
Time
1.5
6.5