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Электронный компонент: 74ABT16543

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October 1993
Revised January 1999
7
4
AB
T1
6543 1
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1999 Fairchild Semiconductor Corporation
DS011646.prf
www.fairchildsemi.com
74ABT16543
16-Bit Registered Transceiver with 3-STATE Outputs
General Description
The ABT16543 16-bit transceiver contains two sets of D-
type latches for temporary storage of data flowing in either
direction. Separate Latch Enable and Output Enable inputs
are provided for each register to permit independent con-
trol of inputting and outputting in either direction of data
flow. Each byte has separate control inputs, which can be
shorted together for full 16-bit operation.
Features
s
Back-to-back registers for storage
s
Bidirectional data path
s
A and B outputs have current sourcing capability of 32
mA and current sinking capability of 64 mA
s
Separate control logic for each byte
s
16-bit version of the ABT543
s
Separate controls for data flow in each direction
s
Guaranteed latchup protection
s
High impedance glitch free bus loading during entire
power up and power down cycle
s
Nondestructive hot insertion capability
Ordering Code:
Devices also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Assignment for SSOP and TSSOP
Pin Descriptions
Order Number
Package Number
Package Description
74ABT16543CSSC MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74ABT16543CMTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names
Description
OEAB
n
A-to-B Output Enable Input (Active LOW)
OEBA
n
B-to-A Output Enable Input (Active LOW)
CEAB
n
A-to-B Enable Input (Active LOW)
CEBA
n
B-to-A Enable Input (Active LOW)
LEAB
n
A-to-B Latch Enable Input (Active LOW)
LEBA
n
B-to-A Latch Enable Input (Active LOW)
A
0
A
15
A-to-B Data Inputs or
B-to-A 3-STATE Outputs
B
0
B
15
B-to-A Data Inputs or
A-to-B 3-STATE Outputs
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2
74ABT16543
Logic Symbol
Data I/O Control Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
A-to-B data flow shown;
B-to-A flow control is the same, except using CEBA
n
, LEBA
n
and OEBA
n
Functional Description
The ABT16543 contains two sets of D-type latches, with
separate input and output controls for each. For data flow
from A to B, for example, the A to B Enable (CEAB) input
must be low in order to enter data from the A port or take
data from the B-Port as indicated in the Data I/O Control
Table. With CEAB low, a low signal on (LEAB) input makes
the A to B latches transparent; a subsequent low to high
transition of the LEAB line puts the A latches in the storage
mode and their outputs no longer change with the A inputs.
With CEAB and OEAB both low, the B output buffers are
active and reflect the data present on the output of the A
latches. Control of data flow from B to A is similar, but using
the CEBA, LEBA and OEBA. Each byte has separate con-
trol inputs, allowing the device to be used as two 8-bit
transceivers or as one 16-bit transceiver.
Logic Diagrams
Byte 1 (0:7)
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
Byte 2 (8:15)
Please note that this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
Inputs
Latch Status Output Buffers
CEAB
n
LEAB
n
OEAB
n
(Byte n)
(Byte n)
H
X
X
Latched
HIGH Z
X
H
X
Latched
--
L
L
X
Transparent
--
X
X
H
--
HIGH Z
L
X
L
--
Driving
3
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7
4
AB
T1
6543
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Note 3: Guaranteed but not tested.
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
55
C to
+
125
C
Junction Temperature under Bias
-
55
C to
+
150
C
V
CC
Pin Potential to
Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 2)
-
0.5V to
+
7.0V
Input Current (Note 2)
-
30 mA to
+
5.0 mA
Voltage Applied to Any Output
in the Disable or
Power-Off State
-
0.5V to
+
5.5V
in the HIGH State
-
0.5V to V
CC
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
DC Latchup Source Current
-
500 mA
Over Voltage Latchup (I/O)
10V
Free Air Ambient Temperature
-
40
C to
+
85
C
Supply Voltage
+
4.5V to
+
5.5V
Minimum Input Edge Rate (
V/
t)
Data Input
50 mV/ns
Enable Input
20 mV/ns
Clock Input
100 mV/ns
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
Min
I
IN
=
-
18 mA (Non I/O Pins)
V
OH
Output HIGH Voltage
2.5
I
OH
=
-
3 mA, (A
n
, B
n
)
2.0
I
OH
=
-
32 mA, (A
n
, B
n
)
V
OL
Output LOW Voltage
0.55
V
Min
I
OL
=
64 mA, (A
n
, B
n
)
V
ID
Input Leakage Test
4.75
V
0.0
I
ID
=
1.9
A, (Non-I/O Pins)
All Other Pins Grounded
I
IH
Input HIGH Current
1
A
Max
V
IN
=
2.7V (Non-I/O Pins) ((Note 3)
1
V
IN
=
V
CC
(Non-I/O Pins)
I
BVI
Input HIGH Current Breakdown Test
7
A
Max
V
IN
=
7.0V (Non-I/O Pins)
I
BVIT
Input HIGH Current
100
A
Max
V
IN
=
5.5V (A
n
, B
n
)
Breakdown Test (I/O)
I
IL
Input LOW Current
-
1
A
Max
V
IN
=
0.5V (Non-I/O Pins) (Note 3)
-
1
V
IN
=
0.0V (Non-I/O Pins)
I
IH
+
I
OZH
Output Leakage Current
10
A
0V5.5V V
OUT
=
2.7V (A
n
, B
n
);
OEAB or CEAB
=
2V
I
IL
+
I
OZL
Output Leakage Current
-
10
A
0V5.5V V
OUT
=
0.5V (A
n
, B
n
);
OEAB or CEAB
=
2V
I
OS
Output Short-Circuit Current
-
100
-
275
mA
Max
V
OUT
=
0V (A
n
, B
n
)
I
CEX
Output HIGH Leakage Current
50
A
Max
V
OUT
=
V
CC
(A
n
, B
n
)
I
ZZ
Bus Drainage Test
100
A
0.0V
V
OUT
=
5.5V (A
n
, B
n
); All Others GND
I
CCH
Power Supply Current
1.0
mA
Max
All Outputs HIGH
I
CCL
Power Supply Current
60
mA
Max
All Outputs LOW
I
CCZ
Power Supply Current
1.0
mA
Max
Outputs 3-STATE
All Others at V
CC
or GND
I
CCT
Additional I
CC
/Input
2.5
mA
Max
V
I
=
V
CC
-
2.1V
All Others at V
CC
or GND
I
CCD
Dynamic I
CC
No Load
Outputs Open, CEAB, OEAB, LEAB
=
GND,
(Note 3)
0.25
mA/MHz
Max
CEBA
=
V
CC
, One Bit Toggling,
50% Duty Cycle
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4
74ABT16543
AC Electrical Characteristics
AC Operating Requirements
(SSOP Package)
Capacitance
Note 4: C
I/O
is measured at frequency, f
=
1 MHz, per MIL-STD-883, Method 3012.
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
55
C to
+
85
C
Units
V
CC
=
+
5.0V
V
CC
=
4.5V5.5V
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay
1.5
3.0
5.7
1.5
5.7
ns
t
PHL
A
n
to B
n
or B
n
to A
n
t
PLH
Propagation Delay
1.5
3.0
5.5
1.5
5.5
ns
t
PHL
LEAB
n
to B
n
, LEBA
n
to A
n
t
PZH
Enable Time
1.5
2.8
5.2
1.5
5.2
ns
t
PZL
OEBA
n
or OEAB
n
to A
n
or B
n
t
PHZ
Disable Time
1.6
3.1
6.0
1.6
6.0
ns
t
PLZ
OEAB
n
or OEBA
n
to A
n
or B
n
t
PZH
Enable Time
1.5
3.1
6.2
1.5
6.2
ns
t
PZL
CEBA
n
or CEAB
n
to A
n
or B
n
t
PHZ
Disable Time
1.7
3.2
6.3
1.7
6.3
ns
t
PLZ
CEBA
n
or CEAB
n
to A
n
or B
n
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
55
C to
+
85
C
Units
V
CC
=
+
5.0V
V
CC
=
4.5V5.5V
C
L
=
50 pF
C
L
=
50 pF
Min
Max
Min
Max
t
S
(H)
Setup Time, HIGH or LOW
2.0
2.0
ns
t
S
(L)
A
n
or B
n
to LEBA
n
or LEAB
n
2.0
2.0
t
H
(H)
Hold Time, HIGH or LOW
1.0
1.0
ns
t
H
(L)
A
n
or B
n
to LEBA
n
or LEAB
n
1.0
1.0
t
W
(L)
Pulse Width, LOW
3.0
3.0
ns
Symbol
Parameter
Typ
Units
Conditions
T
A
=
25
C
C
IN
Input Capacitance
5.0
pF
V
CC
=
0V (non I/O pins)
C
I/O
(Note 4)
Output Capacitance
11.0
pF
V
CC
=
5.0V (A
n
, B
n
)
5
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7
4
AB
T1
6543
AC Loading
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
FIGURE 2. V
M
=
1.5V
Input Pulse Requirements
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 4. Propagation Delay Waveforms
for Inverting and Non-Inverting Functions
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
FIGURE 6. 3-STATE Output HIGH
and LOW Enable and Disable Times
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
Amplitude
Rep. Rate
t
W
t
r
t
f
3V
1 MHz
500 ns
2.5 ns
2.5 ns