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Электронный компонент: 74ABT16652CMTD

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April 1993
Revised January 1999
7
4
AB
T1
6652
1
6
-Bi
t
T
r
a
nsceiv
e
r
s
and Regist
er
s
wi
th 3-
S
T
A
T
E
Out
puts
1999 Fairchild Semiconductor Corporation
DS011599.prf
www.fairchildsemi.com
74ABT16652
16-Bit Transceivers and Registers with 3-STATE Outputs
General Description
The ABT16652 consists of sixteen bus transceiver circuits
with D-type flip-flops, and control circuitry arranged for mul-
tiplexed transmission of data directly from the input bus or
from the internal registers. Each byte has separate control
inputs which can be shorted together for full 16-bit opera-
tion. Data on the A or B bus will be clocked into the regis-
ters as the appropriate clock pin goes to HIGH logic level.
Output Enable pins (OEAB, OEBA) are provided to control
the transceiver function.
Features
s
Independent registers for A and B buses
s
Multiplexed real-time and stored data
s
Separate control logic for each byte
s
A and B output sink capability of 64 mA, source
capability of 32 mA
s
Guaranteed output skew
s
High impedance glitch free bus loading during entire
power up and power down cycle
s
Nondestructive hot insertion capability
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Pin Descriptions
Connection Diagram
Order Number
Package Number
Package Description
74ABT16652CSSC MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74ABT16652CMTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names
Descriptions
A
0
A
16
Data Register A Inputs/
3-STATE Outputs
B
0
B
16
Data Register B Inputs/
3-STATE Outputs
CPAB
n
, CPBA
n
Clock Pulse Inputs
SAB
n
, SBA
n
Select Inputs
OEAB
n
, OEBA
n
Output Enable Inputs
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2
74ABT16652
Functional Description
In the transceiver mode, data present at the HIGH imped-
ance port may be stored in either the A or B register or
both.
The select (SAB
n
, SBA
n
) controls can multiplex stored and
real-time.
The examples in
Figure 1 demonstrate the four fundamen-
tal bus-management functions that can be performed with
the ABT16652.
Data on the A or B data bus, or both can be stored in the
internal D flip-flop by LOW to HIGH transitions at the
appropriate Clock Inputs (CPAB
n
, CPBA
n
) regardless of
the Select or Output Enable Inputs. When SAB and SBA
are in the real time transfer mode, it is also possible to
store data without using the internal D flip-flops by simulta-
neously enabling OEAB
n
and OEBA
n
. In this configuration
each Output reinforces its Input. Thus when all other data
sources to the two sets of bus lines are in a HIGH imped-
ance state, each set of bus lines will remain at its last state.
Note A: Real-Time
Transfer Bus B to Bus A
Note B: Real-Time
Transfer Bus A to Bus B
Note C: Storage
Note D: Transfer Storage
Data to A or B
FIGURE 1.
OEAB
1
OEBA
1
CPAB
1
CPBA
1
SAB
1
SBA
1
L
L
X
X
X
L
OEAB
1
OEBA
1
CPAB
1
CPBA
1
SAB
1
SBA
1
H
H
X
X
L
X
OEAB
1
OEBA
1
CPAB
1
CPBA
1
SAB
1
SBA
1
X
H
X
X
X
L
X
X
X
X
L
H
X
X
OEAB
1
OEBA
1
CPAB
1
CPBA
1
SAB
1
SBA
1
H
L
H or L
H or L
H
H
3
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7
4
AB
T1
6652
Function Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW to HIGH Clock Transition
Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e.,
data at the bus pins will be stored on every LOW to HIGH transition on the clock inputs. This also applies to data I/O (A and B: 815) and #2 control pins.
Logic Diagrams
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs
Inputs/Outputs (Note 1)
Operating Mode
OEAB
1
OEBA
1
CPAB
1
CPBA
1
SAB
1
SBA
1
A
0
thru A
7
B
0
thru B
7
L
H
H or L
H or L
X
X
Input
Input
Isolation
L
H
X
X
Store A and B Data
X
H
H or L
X
X
Input
Not Specified Store A, Hold B
H
H
X
X
Input
Output
Store A in Both Registers
L
X
H or L
X
X
Not Specified Input
Hold A, Store B
L
L
X
X
Output
Input
Store B in Both Registers
L
L
X
X
X
L
Output
Input
Real-Time B Data to A Bus
L
L
X
H or L
X
H
Store B Data to A Bus
H
H
X
X
L
X
Input
Output
Real-Time A Data to B Bus
H
H
H or L
X
H
X
Stored A Data to B Bus
H
L
H or L
H or L
H
H
Output
Output
Stored A Data to B Bus and
Stored B Data to A Bus
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4
74ABT16652
Absolute Maximum Ratings
(Note 2)
Recommended Operating
Conditions
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 3: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Note 4: Guaranteed but not tested.
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
55
C to
+
125
C
Junction Temperature under Bias
-
55
C to
+
150
C
V
CC
Pin Potential to
Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 3)
-
0.5V to
+
7.0V
Input Current (Note 3)
-
30 mA to
+
5.0 mA
Voltage Applied to Any Output
in the Disable or Power-Off State
-
0.5V to
+
5.5V
in the HIGH State
-
0.5V to V
CC
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
DC Latchup Source Current
-
500 mA
Over Voltage Latchup (I/O)
10V
Free Air Ambient Temperature
-
40
C to
+
85
C
Supply Voltage
+
4.5V to
+
5.5V
Minimum Input Edge Rate (
V/
t)
Data Input
50 mV/ns
Enable Input
20 mV/ns
Clock Input
100 mV/ns
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
V
Recognized HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
Min
I
IN
=
-
18 mA (Non I/O Pins)
V
OH
Output HIGH
2.5
V
Min
I
OH
=
-
3 mA, (A
n
, B
n
)
Voltage
2.0
I
OH
=
-
32 mA, (A
n
, B
n
)
V
OL
Output LOW Voltage
0.55
V
Min
I
OL
=
64 mA, (A
n
, B
n
)
V
ID
Input Leakage Test
V
0.0
I
ID
=
1.9
A, (Non-I/O Pins)
All Other Pins Grounded
I
IH
Input HIGH Current
1
A
Max
V
IN
=
2.7V (Non-I/O Pins) (Note 4)
1
V
IN
=
V
CC
(Non-I/O Pins)
I
BVI
Input HIGH Current
7
A
Max
V
IN
=
7.0V (Non-I/O Pins)
Breakdown Test
I
BVIT
Input HIGH Current
100
A
Max
V
IN
=
5.5V (A
n
, B
n
)
Breakdown Test (I/O)
I
IL
Input LOW Current
-
1
A
Max
V
IN
=
0.5V (Non-I/O Pins) (Note 4)
-
1
V
IN
=
0.0V (Non-I/O Pins)
I
IH
+
I
OZH
Output Leakage Current
10
A
0V5.5V V
OUT
=
2.7V (A
n
, B
n
);
OEAB
n
=
GND and OEBA
n
=
2.0V
I
IL
+
I
OZL
Output Leakage Current
-
10
A
0V5.5V
V
OUT
=
0.5V (A
n
, B
n
);
OEAB
n
=
GND and OEBA
n
=
2.0V
I
OS
Output Short-Circuit Current
-
275
mA
Max
V
OUT
=
0V (A
n
, B
n
)
I
CEX
Output HIGH Leakage Current
50
A
Max
V
OUT
=
V
CC
(A
n
, B
n
)
I
ZZ
Bus Drainage Test
100
A
0.0V
V
OUT
=
5.5V (A
n
, B
n
); All Others GND
I
CCH
Power Supply Current
1.0
mA
Max
All Outputs HIGH
I
CCL
Power Supply Current
60
mA
Max
All Outputs LOW
I
CCZ
Power Supply Current
1.0
mA
Max
Outputs 3-STATE;
All Others at V
CC
or GND
I
CCT
Additional I
CC
/Input
2.5
mA
Max
V
I
=
V
CC
-
2.1V
All Others at V
CC
or GND
I
CCD
Dynamic I
CC
No Load
0.23
mA/MHz
Max
Outputs Open
(Note 4)
OEAB
n
, OEBA
n
and SEL
=
GND
Non-I/O
=
GND or V
CC
One bit toggling, 50% duty cycle
5
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7
4
AB
T1
6652
DC Electrical Characteristics
(SSOP Package)
Note 5: Max number of outputs defined as (n). n
-
1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 6: Max number of outputs defined as (n). n
-
1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
Note 7: Max number of data inputs (n) switching. n
-
1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V
ILD
), 0V to threshold (V
IHD
).
Guaranteed, but not tested.
AC Electrical Characteristics
(SSOP Package)
AC Operating Requirements
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
C
L
=
50 pF, R
L
=
500
V
OLP
Quiet Output Maximum Dynamic V
OL
0.7
1.2
V
5.0
T
A
=
25
C (Note 5)
V
OLV
Quiet Output Minimum Dynamic V
OL
-
1.4
-
1.0
V
5.0
T
A
=
25
C (Note 5)
V
OHV
Minimum HIGH Level Dynamic Output Voltage
2.5
3.0
V
5.0
T
A
=
25
(Note 6)
V
IHD
Minimum HIGH Level Dynamic Input Voltage
2.0
1.6
V
5.0
T
A
=
25
C (Note 7)
V
ILD
Maximum LOW Level Dynamic Input Voltage
1.2
0.8
V
5.0
T
A
=
25
C (Note 7)
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Units
V
CC
=
+
5.0V
V
CC
=
4.5V5.5V
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay
1.5
3.0
4.9
1.5
4.9
ns
t
PHL
Clock to Bus
1.5
3.4
4.9
1.5
4.9
t
PLH
Propagation Delay
1.5
2.6
4.5
1.5
4.5
ns
t
PHL
Bus to Bus
1.5
3.0
4.5
1.5
4.5
t
PLH
Propagation Delay
1.5
2.9
5.0
1.5
5.0
ns
t
PHL
SBA
n
or SAB
n
1.5
3.2
5.0
1.5
5.0
to A
n
to B
n
t
PZH
Enable Time
1.5
2.8
5.5
1.5
5.5
ns
t
PZL
OEBA
n
or OEAB
n
1.5
3.0
5.5
1.5
5.5
to A
n
or B
n
t
PHZ
Disable Time
1.5
3.9
5.9
1.5
5.9
ns
t
PLZ
OEBA
n
or OEAB
n
1.5
3.3
5.9
1.5
5.9
to A
n
or B
n
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Units
V
CC
=
+
5.0V
V
CC
=
4.5V5.5V
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
f
max
Max Clock Frequency
200
MHz
t
S
(H)
Setup Time, HIGH
2.0
2.0
ns
t
S
(L)
or LOW Bus to Clock
t
H
(H)
Hold Time, HIGH
1.0
1.0
ns
t
H
(L)
or LOW Bus to Clock
t
W
(H)
Pulse Width,
3.0
3.0
ns
t
W
(L)
HIGH or LOW