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Электронный компонент: 74ABT240CSC

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1999 Fairchild Semiconductor Corporation
DS011664
www.fairchildsemi.com
March 1994
Revised November 1999
7
4
AB
T2
40 Oct
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Buff
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L
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3-ST
A
T
E Outp
uts
74ABT240
Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The ABT240 is an inverting octal buffer and line driver
designed to be employed as a memory address driver,
clock driver and bus oriented transmitter or receiver which
provides improved PC board density.
Features
s
Output sink capability of 64 mA, source capability of
32 mA
s
Guaranteed latchup protection
s
High impedance glitch free bus loading during entire
power up and power down cycle
s
Nondestructive hot insertion capability
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Pin Descriptions
Truth Tables
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
Order Number
Package Number
Package Description
74ABT240CSC M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body
74ABT240CSJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT240CMSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT240CMTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names
Description
OE
1
, OE
2
3-STATE Output
Enable Inputs
I
0
I
7
Inputs
O
0
O
7
Outputs
Inputs
Outputs
(Pins 12, 14, 16, 18)
OE
1
I
n
L
L
H
L
H
L
H
X
Z
Inputs
Outputs
(Pins 3, 5, 7, 9)
OE
2
I
n
L
L
H
L
H
L
H
X
Z
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2
74ABT240
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Note 3: Guaranteed, but not tested.
Note 4: For 8 bits toggling, I
CCD
<
0.8 mA/MHz.
Storage Temperature
-
65
C to
+
150
C
Junction Temperature under Bias
-
55
C to
+
150
C
V
CC
Pin Potential to Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 2)
-
0.5V to
+
7.0V
Input Current (Note 2)
-
30 mA to
+
5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-Off State
-
0.5V to 5.5V
in the HIGH State
-
0.5V to V
CC
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
DC Latchup Source Current
(Across Comm Operating Range)
-
150 mA
Over Voltage Latchup (I/O)
10V
Free Air Ambient Temperature
-
40
C to
+
85
C
Supply Voltage
+
4.5V to
+
5.5V
Minimum Input Edge Rate (
V/
t)
Data Input
50 mV/ns
Enable Input
20 mV/ns
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
Min
I
IN
=
-
18 mA
V
OH
Output HIGH Voltage
2.5
V
Min
I
OH
=
-
3 mA
2.0
V
Min
I
OH
=
-
32 mA
V
OL
Output LOW Voltage
0.55
V
Min
I
OL
=
64 mA
I
IH
Input HIGH Current
1
A
Max
V
IN
=
2.7V (Note 3)
1
V
IN
=
V
CC
I
BVI
Input HIGH Current Breakdown Test
7
A
Max
V
IN
=
7.0V
I
IL
Input LOW Current
-
1
A
Max
V
IN
=
0.5V (Note 3)
-
1
V
IN
=
0.0V
V
ID
Input Leakage Test
4.75
V
0.0
I
ID
=
1.9
A
All Other Pins Grounded
I
OZH
Output Leakage Current
10
A
0
-
5.5V
V
OUT
=
2.7V; OE
n
=
2.0V
I
OZL
Output Leakage Current
-
10
A
0
-
5.5V
V
OUT
=
0.5V; OE
n
=
2.0V
I
OS
Output Short-Circuit Current
-
100
-
275
mA
Max
V
OUT
=
0.0V
I
CEX
Output HIGH Leakage Current
50
A
Max
V
OUT
=
V
CC
I
ZZ
Bus Drainage Test
100
A
0.0
V
OUT
=
5.5V; All Others GND
I
CCH
Power Supply Current
50
A
Max
All Outputs HIGH
I
CCL
Power Supply Current
30
mA
Max
All Outputs LOW
I
CCZ
Power Supply Current
50
A
Max
OE
n
=
V
CC
;
All Others at V
CC
or Ground
I
CCT
Additional I
CC
/Input
Outputs Enabled
1.5
mA
Max
V
I
=
V
CC
-
2.1V
Outputs 3-STATE
1.5
mA
Enable Input V
I
=
V
CC
-
2.1V
Outputs 3-STATE
50
A
Data Input V
I
=
V
CC
-
2.1V
All Others at V
CC
or Ground
I
CCD
Dynamic I
CC
No Load
mA/
Max
Outputs Open
(Note 3)
0.1
MHz
OE
n
=
GND, (Note 4)
One Bit Toggling, 50% Duty Cycle
3
www.fairchildsemi.com
74
A
B
T
2
4
0
AC Electrical Characteristics
Capacitance
Note 5: C
OUT
is measured at frequency f
=
1 MHz, per MIL-STD-883, Method 3012.
T
A
=
+
25
C
T
A
=
-
55
C to
+
125
C
T
A
=
-
40
C to
+
85
C
V
CC
=
+
5V
V
CC
=
4.5V5.5V
V
CC
=
4.5V5.5V
Symbol
Parameter
C
L
=
50 pF
C
L
=
50 pF
C
L
=
50 pF
Units
Min
Typ
Max
Min
Max
Min
Max
t
PLH
Propagation Delay
1.0
4.8
0.8
5.5
1.0
4.8
ns
t
PHL
Data to Outputs
1.6
4.8
1.0
5.5
1.6
4.8
t
PZH
Output Enable
1.1
6.2
0.8
7.5
1.1
6.2
ns
t
PZL
Time
1.1
6.2
0.8
7.7
1.1
6.2
t
PHZ
Output Disable
1.8
6.4
1.0
7.5
1.8
6.4
ns
t
PLZ
Time
1.6
5.8
1.0
7.2
1.6
5.8
Symbol
Parameter
Typ
Units
Conditions
T
A
=
25
C
C
IN
Input Capacitance
5.0
pF
V
CC
=
0V
C
OUT
(Note 5)
Output Capacitance
9.0
pF
V
CC
=
5.0V
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4
74ABT240
AC Loading
*Includes jig and probe capacitance
Standard AC Test Load
Test Input Signal Levels
Test Input Signal Requirements
AC Waveforms
Propagation Delay,
Pulse Width Waveforms
3-STATE Output HIGH
and LOW Enable and Disable Times
Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
Setup Time, Hold Time
and Recovery Time Waveforms
Amplitude
Rep. Rate
t
W
t
r
t
f
3.0V
1 MHz
500 ns
2.5 ns
2.5 ns
5
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74
A
B
T
2
4
0
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body
Package Number M20B