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Электронный компонент: 74ABT245CSC

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1999 Fairchild Semiconductor Corporation
DS010945
www.fairchildsemi.com
September 1991
Revised November 1999
7
4
AB
T2
45 Oct
a
l
Bi-
D
ir
ecti
onal
T
r
anscei
ver
wit
h
3-
ST
A
T
E
Output
s
74ABT245
Octal Bi-Directional Transceiver with 3-STATE Outputs
General Description
The ABT245 contains eight non-inverting bidirectional buff-
ers with 3-STATE outputs and is intended for bus-oriented
applications. Current sinking capability is 64 mA on both
the A and B ports. The Transmit/Receive (T/R) input deter-
mines the direction of data flow through the bidirectional
transceiver. Transmit (active HIGH) enables data from A
Ports to B Ports; Receive (active LOW) enables data from
B Ports to A Ports. The Output Enable input, when HIGH,
disables both A and B ports by placing them in a HIGH Z
condition.
Features
s
Bidirectional non-inverting buffers
s
A and B output sink capability of 64 mA, source
capability of 32 mA
s
Guaranteed output skew
s
Guaranteed multiple output switching specifications
s
Output switching specified for both 50 pF and 250 pF
loads
s
Guaranteed simultaneous switching, noise level and
dynamic threshold performance
s
Guaranteed latchup protection
s
High impedance glitch-free bus loading during entire
power up and power down cycle
s
Non-destructive hot insertion capability
s
Disable time is less than enable time to avoid bus
contention
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Pin Descriptions
Order Number
Package Number
Package Description
74ABT245CSC M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body
74ABT245CSJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT245CMSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT245CMTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ABT245CPC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Pin Names
Description
OE
Output Enable Input (Active LOW)
T/R
Transmit/Receive Input
A
0
A
7
Side A Inputs or 3-STATE Outputs
B
0
B
7
Side B Inputs or 3-STATE Outputs
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2
74ABT245
Logic Symbol
Truth Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Logic Diagram
Inputs
Output
OE
T/R
L
L
Bus B Data to Bus A
L
H
Bus A Data to Bus B
H
X
HIGH Z State
3
www.fairchildsemi.com
74
A
B
T
2
4
5
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs
DC Electrical Characteristics
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
55
C to
+
125
C
Junction Temperature under Bias
-
55
C to
+
150
C
V
CC
Pin Potential to Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 2)
-
0.5V to
+
7.0V
Input Current (Note 2)
-
30 mA to
+
5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-off
State
-
0.5V to 5.5V
in the HIGH State
-
0.5V to V
CC
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
DC Latchup Source Current
-
500 mA
Over Voltage Latchup (I/O)
10V
Free Air Ambient Temperature
-
40
C to
+
85
C
Supply Voltage
+
4.5V to
+
5.5V
Minimum Input Edge Rate (
V/
t)
Data Input
50 mV/ns
Enable Input
20 mV/ns
Symbol
Parameter Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
Min
I
IN
=
-
18 mA (OE, T/R)
V
OH
Output HIGH Voltage
2.5
V
Min
I
OH
=
-
3 mA (A
n
, B
n
)
2.0
V
Min
I
OH
=
-
32 mA (A
n
, B
n
)
V
OL
Output LOW Voltage
0.55
V
Min
I
OL
=
64 mA (A
n
, B
n
)
I
IH
Input HIGH Current
1
A
Max
V
IN
=
2.7V (OE, T/R)
1
V
IN
=
V
CC
(OE, T/R)
I
BVI
Input HIGH Current Breakdown Test
7
A
Max
V
IN
=
7.0V (OE, T/R)
I
BVIT
Input HIGH Current Breakdown Test (I/O)
100
A
Max
V
IN
=
5.5V (A
n
, B
n
)
I
IL
Input LOW Current
-
1
A
Max
V
IN
=
0.5V (OE, T/R)
-
1
V
IN
=
0.0V (OE, T/R)
V
ID
Input Leakage Test
4.75
V
0.0
I
ID
=
1.9
A (OE, T/R)
All Other Pins Grounded
I
IH
+
I
OZH
Output Leakage Current
10
A
0
-
5.5V
V
OUT
=
2.7V (A
n
, B
n
); OE
=
2.0V
I
IL
+
I
OZL
Output Leakage Current
-
10
A
0
-
5.5V
V
OUT
=
0.5V (A
n
, B
n
); OE
=
2.0V
I
OS
Output Short-Circuit Current
-
100
-
275
mA
Max
V
OUT
=
0.0V (A
n
, B
n
)
I
CEX
Output HIGH Leakage Current
50
A
Max
V
OUT
=
V
CC
(A
n
, B
n
)
I
ZZ
Bus Drainage Test
100
A
0.0
V
OUT
=
5.5V (A
n
, B
n
);
All Others GND
I
CCH
Power Supply Current
50
A
Max
All Outputs HIGH
I
CCL
Power Supply Current
30
mA
Max
All Outputs LOW
I
CCZ
Power Supply Current
50
A
Max
OE
=
V
CC
, T/R
=
GND or V
CC
;
All Other GND or V
CC
I
CCT
Additional
Outputs Enabled
2.5
mA
V
I
=
V
CC
-
2.1V
I
CC
/Input
Outputs 3-STATE
2.5
mA
Max
OE, T/R V
I
=
V
CC
-
2.1V
Outputs 3-STATE
50
A
Data Input V
I
=
V
CC
-
2.1V
All Others at V
CC
or GND.
I
CCD
Dynamic I
CC
No Load
0.1
mA/
Max
Outputs Open
MHz
OE
=
GND, T/R
=
GND or V
CC
One Bit Toggling, 50% Duty Cycle
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4
74ABT245
DC Electrical Characteristics
(SOIC package)
Note 3: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 4: Max number of data inputs (n) switching. n-1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V
ILD
), 0V to threshold (V
IHD
).
Guaranteed, but not tested.
Note 5: Max number of outputs defined as (n). n
-
1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and SSOP package)
Extended AC Electrical Characteristics
(SOIC package)
Note 6: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 7: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac-
itors in the standard AC load. This specification pertains to single output switching only.
Note 8: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 9: The 3-STATE delays are dominated by the RC network (500
, 250 pF) on the output and have been excluded from the datasheet.
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
C
L
=
50 pF, R
L
=
500
V
OLP
Quiet Output Maximum Dynamic V
OL
0.7
1.0
V
5.0
T
A
=
25
C (Note 3)
V
OLV
Quiet Output Minimum Dynamic V
OL
-
1.3
-
1.0
V
5.0
T
A
=
25
C (Note 3)
V
OHV
Minimum HIGH Level Dynamic Output Voltage
2.7
3.1
V
5.0
T
A
=
25
C (Note 5)
V
IHD
Minimum HIGH Level Dynamic Input Voltage
2.0
1.7
V
5.0
T
A
=
25
C (Note 4)
V
ILD
Maximum LOW Level Dynamic Input Voltage
0.9
0.6
V
5.0
T
A
=
25
C (Note 4)
T
A
=
+
25
C
T
A
=
-
55
C to
+
125
C
T
A
=
-
40
C to
+
85
C
Symbol
Parameter
V
CC
=
+
5V
V
CC
=
4.5V5.5V
V
CC
=
4.5V5.5V
Units
C
L
=
50 pF
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
Min
Max
t
PLH
Propagation Delay
1.0
2.1
3.6
1.0
4.8
1.0
3.6
ns
t
PHL
Data to Outputs
1.0
2.4
3.6
1.0
4.8
1.0
3.6
t
PZH
Output Enable
1.5
3.2
6.0
1.0
6.7
1.5
6.0
ns
t
PZL
Time
1.5
3.7
6.0
2.0
7.5
1.5
6.0
t
PHZ
Output Disable
1.0
3.6
6.1
1.7
7.4
1.0
6.1
ns
t
PLZ
Time
1.0
3.3
5.6
1.7
6.5
1.0
5.6
Symbol
Parameter
-
40
C to
+
85
C
T
A
=
-
40
C to
+
85
C
T
A
=
-
40
C to
+
85
C
Units
V
CC
=
4.5V5.5V
V
CC
=
4.5V5.5V
V
CC
=
4.5V5.5V
C
L
=
50 pF
C
L
=
250 pF
C
L
=
250 pF
8 Outputs Switching
1 Output Switching
8 Outputs Switching
(Note 6)
(Note 7)
(Note 8)
Min
Typ
Max
Min
Max
Min
Max
f
TOGGLE
Max Toggle Frequency
100
MHz
t
PLH
Propagation Delay
1.5
5.0
1.5
6.0
2.5
8.5
ns
t
PHL
Data to Outputs
1.5
5.0
1.5
6.0
2.5
8.5
t
PZH
Output Enable Time
1.5
6.5
2.5
7.5
2.5
9.5
ns
t
PZL
1.5
6.5
2.5
7.5
2.5
11.0
t
PHZ
Output Disable Time
1.0
6.5
(Note 9)
(Note 9)
ns
t
PLZ
1.0
5.6
5
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74
A
B
T
2
4
5
Skew
(SOIC package)
Note 10: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (t
OSHL
), LOW
-
to
-
HIGH (t
OSLH
), or any combination switching LOW
-
to
-
HIGH and/or
HIGH
-
to
-
LOW (t
OST
). The specification is guaranteed but not tested.
Note 11: Propagation delay variation for a given set of conditions (i.e., temperature and V
CC
) from device to device. This specification is guaranteed but not
tested.
Note 12: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.)
Note 13: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 14: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Capacitance
Note 15: C
I/O
is measured at frequency f
=
1 MHz, per MIL-STD-883, Method 3012.
Symbol
Parameter
T
A
=
-
40
C to
+
85
C
T
A
=
-
40
C to
+
85
C
Units
V
CC
=
4.5V5.5V
V
CC
=
4.5V5.5V
C
L
=
50 pF
C
L
=
250 pF
8 Outputs Switching
8 Outputs Switching
(Note 12)
(Note 13)
Max
Max
t
OSHL
Pin to Pin Skew
1.3
2.3
ns
(Note 10)
HL Transitions
t
OSLH
Pin to Pin Skew
1.0
1.8
ns
(Note 10)
LH Transitions
t
PS
Duty Cycle
2.0
3.5
ns
(Note 14)
LHHL Skew
t
OST
Pin to Pin Skew
2.0
3.5
ns
(Note 10)
LH/HL Transitions
t
PV
Device to Device Skew
2.0
3.5
ns
(Note 11)
LH/HL Transitions
Symbol
Parameter
Typ
Units
Conditions
T
A
=
25
C
C
IN
Input Capacitance
5.0
pF
V
CC
=
0V (OE, T/R)
C
I/O
(Note 15)
I/O Capacitance
11.0
pF
V
CC
=
5.0V (A
n
, B
n
)