1999 Fairchild Semiconductor Corporation
DS011549
www.fairchildsemi.com
January 1993
Revised November 1999
7
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AB
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74ABT273
Octal D-Type Flip-Flop
General Description
The ABT273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop's Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements.
Features
s
Eight edge-triggered D-type flip-flops
s
Buffered common clock
s
Buffered, asynchronous Master Reset
s
See ABT377 for clock enable version
s
See ABT373 for transparent latch version
s
See ABT374 for 3-STATE version
s
Output sink capability of 64 mA, source capability of
32 mA
s
Guaranteed latchup protection
s
High impedance glitch free bus loading during entire
power up and power down cycle
s
Non-destructive hot insertion capability
s
Disable time less than enable time to avoid bus conten-
tion
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Pin Descriptions
Order Number
Package Number
Package Description
74ABT273CSC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body
74ABT273CSJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT273CMSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT273CMTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names
Description
D
0
D
7
Data Inputs
MR
Master Reset (Active LOW)
CP
Clock Pulse Input (Active Rising Edge)
Q
0
Q
7
Data Outputs
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74ABT273
Truth Table
H
=
HIGH Voltage Level steady state
h
=
HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition
L
=
LOW Voltage Level steady state
I
=
LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition
X
=
Immaterial
=
LOW-to-HIGH clock transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Operating Mode
Inputs
Output
MR
CP
D
n
Q
n
Reset (Clear)
L
X
X
L
Load "1"
H
h
H
Load "0"
H
l
L
3
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A
B
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7
3
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Note 3: Guaranteed but not tested.
Note 4: For 8 bits toggling, I
CCD
<
0.5 mA/MHz.
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
55
C to
+
125
C
Junction Temperature under Bias
-
55
C to
+
150
C
V
CC
Pin Potential to Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 2)
-
0.5V to
+
7.0V
Input Current (Note 2)
-
30 mA to
+
5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-Off State
-
0.5V to
+
4.75V
in the HIGH State
-
0.5V to V
CC
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
DC Latchup Source Current
-
500 mA
(Across Comm Operating Range)
Over Voltage Latchup
V
CC
+
4.5V
Free Air Ambient Temperature
-
40
C to
+
85
C
Supply Voltage
+
4.5V to
+
5.5V
Minimum Input Edge Rate (
V/
t)
Data Input
50 mV/ns
Enable Input
20 mV/ns
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
Min
I
IN
=
-
18 mA
V
OH
Output HIGH Voltage
2.5
V
Min
I
OH
=
-
3 mA
2.0
I
OH
=
-
32 mA
V
OL
Output LOW Voltage
0.55
V
Min
I
OL
=
64 mA
I
IH
Input HIGH Current
1
A
Max
V
IN
=
2.7V (Note 3)
1
V
IN
=
V
CC
I
BVI
Input HIGH Current
7
A
Max
V
IN
=
7.0V
Breakdown Test
I
IL
Input LOW Current
-
1
A
Max
V
IN
=
0.5V (Note 3)
-
1
V
IN
=
0.0V
V
ID
Input Leakage Test
4.75
V
0.0
I
ID
=
1.9
A
All Other Pins Grounded
I
OS
Output Short-Circuit Current
-
100
-
275
mA
Max
V
OUT
=
0.0V
I
CEX
Output HIGH Leakage Current
50
A
Max
V
OUT
=
V
CC
I
CCH
Power Supply Current
50
A
Max
All Outputs HIGH
I
CCL
Power Supply Current
30
mA
Max
All Outputs LOW
I
CCT
Maximum I
CC
/Input
Outputs Enabled
1.5
mA
Max
V
I
=
V
CC
-
2.1V
Data Input V
I
=
V
CC
-
2.1V
All Others at V
CC
or GND
I
CCD
Dynamic I
CC
No Load
0.3
mA/
Max
Outputs Open (Note 4)
MHz
One Bit Toggling, 50% Duty Cycle
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4
74ABT273
AC Electrical Characteristics
(SSOIC package)
AC Operating Requirements
Capacitance
(SOIC package)
Note 5: C
OUT
is measured at frequency f
=
1 MHz, per MIL-STD-833, Method 3012.
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
55
C to
+
125
C
T
A
=
-
40
C to
+
85
C
Units
V
CC
=
+
5.0V
V
CC
=
4.5V to 5.5V
V
CC
=
4.5V to 5.5V
C
L
=
50 pF
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
Min
Max
f
MAX
Maximum Clock Frequency
150
200
150
150
MHz
t
PLH
Propagation Delay
2.0
6.0
1.0
7.0
2.0
6.0
ns
t
PHL
CP to O
n
2.8
6.8
1.0
7.5
2.8
6.8
t
PHL
Propagation Delay
2.5
7.4
1.0
8.2
2.5
7.4
ns
MR to O
n
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
55
C to
+
125
C
T
A
=
-
40
C to
+
85
C
Units
V
CC
=
+
5.0V
V
CC
=
4.5V to 5.5V
V
CC
=
4.5V to 5.5V
C
L
=
50 pF
C
L
=
50 pF
C
L
=
50 pF
Min
Max
Min
Max
Min
Max
t
S
(H)
Setup Time, HIGH
2.0
2.0
2.0
ns
t
S
(L)
or LOW D
n
to CP
2.5
2.5
2.5
t
H
(H)
Hold Time, HIGH
1.2
1.4
1.2
ns
t
H
(L)
or LOW D
n
to CP
1.2
1.4
1.2
t
W
(H)
Pulse Width, CP,
3.3
3.3
3.3
ns
t
W
(L)
HIGH or LOW
3.3
3.3
3.3
t
W
(L)
Master Reset Pulse
3.3
3.3
3.3
ns
Width, LOW
t
REC
Recovery Time
2.0
2.0
2.0
ns
MR to CP
Symbol
Parameter
Typ
Units
Conditions
T
A
=
25
C
C
IN
Input Capacitance
5
pF
V
CC
=
0V
C
OUT
(Note 5)
Output Capacitance
9
pF
V
CC
=
5.0V
5
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74
A
B
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AC Loading
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
FIGURE 2. V
M
=
1.5V
Input Pulse Requirements
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 4. Propagation Delay,
Pulse Width Waveforms
FIGURE 5. 3-STATE Output HIGH
and LOW Enable and Disable Times
FIGURE 6. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
Amplitude
Rep. Rate
t
W
t
r
t
f
3.0V
1 MHz
500 ns
2.5 ns
2.5 ns
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