ChipFind - документация

Электронный компонент: 74ABT2952CSPC

Скачать:  PDF   ZIP
1999 Fairchild Semiconductor Corporation
DS010969
www.fairchildsemi.com
January 1992
Revised November 1999
7
4
AB
T2
952 Oct
a
l
Regi
ster
ed T
r
anscei
ver
74ABT2952
Octal Registered Transceiver
General Description
The ABT2952 is an octal registered transceiver. Two 8-bit
back to back registers store data flowing in both directions
between two bidirectional buses. Separate clock, clock
enable and 3-STATE output enable signals are provided for
each register. The output pins are guaranteed to source 32
mA and to sink 64 mA.
Features
s
Separate clock, clock enable and 3-STATE output
enable provided for each register
s
A and B output sink capability of 64 mA source capability
of 32 mA
s
Guaranteed output skew
s
Guaranteed multiple output switching specifications
s
Output switching specified for both 50 pF and 250 pF
loads
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed latchup protection
s
High impedance glitch free bus loading during entire
power up and power down cycle
s
Nondestructive hot insertion capability
Ordering Code:
Device also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Descriptions
Order Number
Package Number
Package Description
74ABT2952CSC M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body
74ABT2952CMSA
MSA24
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT2952CMTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names
Description
A
0
A
7
A-Register Inputs/B-Register
3-STATE Outputs
B
0
B
7
B-Register Inputs/A-Register
3-STATE Outputs
OEA
Output Enable A-Register
CPA
A-Register Clock
CEA
A-Register Clock Enable
OEB
Output Enable B-Register
CPB
B-Register Clock
CEB
B-Register Clock Enable
www.fairchildsemi.com
2
74ABT2952
Truth Table
Output Control
Register Function Table (Applies to A or B Register)
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
HIGH Impedance
=
LOW-to-HIGH Transition
NC
=
No Change
Block Diagram
OE
Internal
Output
Function
Q
H
X
Z
Disable Outputs
L
L
L
Enable Outputs
L
H
H
Inputs
Internal
Function
D
CP
CE
Q
X
X
H
NC
Hold Data
L
L
L
Load Data
H
L
H
3
www.fairchildsemi.com
7
4
AB
T2
952
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Note 3: Guaranteed, but not tested.
Note 4: For 8-bit toggling, I
CCD
<
1.4 mA/MHz.
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
55
C to
+
125
C
Junction Temperature under Bias
-
55
C to
+
150
C
V
CC
Pin Potential to Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 2)
-
0.5V to
+
7.0V
Input Current (Note 2)
-
30 mA to
+
5.0 mA
Voltage Applied to Any Output
in the Disable or
Power-Off State
-
0.5V to
+
5.5V
in the HIGH State
-
0.5V to V
CC
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
DC Latchup Source Current
-
500 mA
Over Voltage Latchup (I/O)
10V
Free Air Ambient Temperature
-
40
C to
+
85
C
Supply Voltage
+
4.5V to
+
5.5V
Minimum Input Edge Rate (
V/
t)
Data Input
50 mV/ns
Enable Input
20 mV/ns
Clock Input
100 mV/ns
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
Min
I
IN
=
-
18 mA (Non I/O Pins)
V
OH
Output HIGH Voltage
2.5
I
OH
=
-
3 mA (A
n
, B
n
)
2.0
I
OH
=
-
32 mA (A
n
, B
n
)
V
OL
Output LOW Voltage
0.55
V
Min
I
OL
=
64 mA (A
n
, B
n
)
V
ID
Input Leakage Test
4.75
V
0.0
I
ID
=
1.9
A (Non-I/O Pins)
All Other Pins Grounded
I
IH
Input HIGH Current
1
A
Max
V
IN
=
2.7V (Non-I/O Pins) (Note 3)
1
V
IN
=
V
CC
(Non-I/O Pins)
I
BVI
Input HIGH Current Breakdown Test
7
A
Max
V
IN
=
7.0V (Non-I/O Pins)
I
BVIT
Input HIGH Current Breakdown Test (I/O)
100
A
Max
V
IN
=
5.5V (A
n
, B
n
)
I
IL
Input LOW Current
-
1
A
Max
V
IN
=
0.5V (Non-I/O Pins) (Note 3)
-
1
V
IN
=
0.0V (Non-I/O Pins)
I
IH
+
I
OZH
Output Leakage Current
10
A
0V5.5V V
OUT
=
2.7V (A
n
, B
n
);
OEA or OEB
=
2.0V
I
IL
+
I
OZL
Output Leakage Current
-
10
A
0V5.5V V
OUT
=
0.5V (A
n
, B
n
);
OEA or OEB
=
2.0V
I
OS
Output Short-Circuit Current
-
100
-
275
mA
Max
V
OUT
=
0V (A
n
, B
n
)
I
CEX
Output HIGH Leakage Current
50
A
Max
V
OUT
=
V
CC
(A
n
, B
n
)
I
ZZ
Bus Drainage Test
100
A
0.0V
V
OUT
=
5.5V (A
n
, B
n
);
All Others GND
I
CCH
Power Supply Current
250
A
Max
All Outputs HIGH
I
CCL
Power Supply Current
30
mA
Max
All Outputs LOW
I
CCZ
Power Supply Current
50
A
Max
Outputs 3-STATE;
All Others GND
I
CCT
Additional I
CC
/Input
2.5
mA
Max
V
I
=
V
CC
-
2.1V; All Others
at V
CC
or GND
I
CCD
Dynamic I
CC
No Load
0.18
mA/MHz
Max
Outputs Open
(Note 4)
OEA or OEB
=
GND,
Non-I/O
=
GND or V
CC
One Bit toggling, 50% duty cycle
(Note 4)
www.fairchildsemi.com
4
74ABT2952
DC Electrical Characteristics
(SOIC Package)
Note 5: Max number of outputs defined as (n). n
-
1 data inputs are driven 0V to 3V. One output at Low. Guaranteed, but not tested.
Note 6: Max number of outputs defined as (n). n
-
1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
Note 7: Max number of data inputs (n) switching. n
-
1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V
ILD
), 0V to threshold (V
IHD
).
Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and SSOP Package)
AC Operating Requirements
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
C
L
=
50 pF,
R
L
=
500
V
OLP
Quiet Output Maximum Dynamic V
OL
0.6
0.8
V
5.0
T
A
=
25
C (Note 5)
V
OLV
Quiet Output Minimum Dynamic V
OL
-
1.2
-
1.0
V
5.0
T
A
=
25
C (Note 5)
V
OHV
Minimum HIGH Level Dynamic Output Voltage
2.5
3.0
V
5.0
T
A
=
25
C (Note 6)
V
IHD
Minimum HIGH Level Dynamic Input Voltage
2.0
1.7
V
5.0
T
A
=
25
C (Note 7)
V
ILD
Maximum LOW Level Dynamic Input Voltage
1.2
0.8
V
5.0
T
A
=
25
C (Note 7)
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Units
V
CC
=
+
5.0V
V
CC
=
4.5V to 5.5V
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
f
MAX
Maximum Clock Frequency
200
200
MHz
t
PLH
Propagation Delay
1.5
3.4
5.3
1.5
5.3
ns
t
PHL
CPA or CPB to
1.5
3.6
5.3
1.5
5.3
A
n
or B
n
t
PZH
Output Enable Time
1.5
3.2
5.5
1.5
5.5
ns
t
PZL
OEA or OEB to
1.5
3.5
5.5
1.5
5.5
A
n
or B
n
t
PHZ
Output Disable Time
1.5
3.6
6.0
1.5
6.0
ns
t
PLZ
OEA or OEB to
1.5
3.2
6.0
1.5
6.0
A
n
or B
n
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Units
V
CC
=
+
5.0V
V
CC
=
4.5V to 5.5V
C
L
=
50 pF
C
L
=
50 pF
Min
Max
Min
Max
t
S
(H)
Setup Time, HIGH
2.5
2.5
ns
t
s
(L)
or LOW A
n
or B
n
2.5
2.5
to CPA or CPB
t
H
(H)
Hold Time, HIGH
1.5
1.5
ns
t
H
(L)
or LOW A
n
or B
n
1.5
1.5
to CPA or CPB
t
S
(H)
Setup Time, HIGH
2.5
2.5
ns
t
S
(L)
or LOW CEA or CEB
2.5
2.5
to CPA or CPB
t
H
(H)
Hold Time, HIGH
1.5
1.5
ns
t
H
(L)
or LOW CEA or CEB
1.5
1.5
to CPA or CPB
t
W
(H)
Pulse Width,
3.0
3.0
ns
t
W
(L)
HIGH or LOW
3.0
3.0
CPA or CPB
5
www.fairchildsemi.com
7
4
AB
T2
952
Extended AC Electrical Characteristics
(SOIC Package)
Note 8: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 9: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 10: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 11: The 3-STATE delays are dominated by the RC network (500
, 250 pF) on the output and has been excluded from the datasheet.
Skew
(SOIC Package)
Note 12: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 13: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (t
OSHL
), LOW to HIGH (t
OSLH
), or any combination switching LOW-to-HIGH and/or HIGH-to-
LOW (t
OST
). This specification is guaranteed but not tested.
Note 15: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Note 16: Propagation delay variation for a given set of conditions (i.e., temperature and V
CC
) from device to device. This specification is guaranteed but not
tested.
Capacitance
Note 17: C
I/O
is measured at frequency f
=
1 MHz, per MIL-STD-883, Method 3012.
Symbol
Parameter
T
A
=
-
40
C to
+
85
C
T
A
=
-
40
C to
+
85
C
T
A
=
-
40
C to
+
85
C
Units
V
CC
=
4.5V to 5.5V
V
CC
=
4.5V to 5.5V
V
CC
=
4.5V to 5.5V
C
L
=
50 pF
C
L
=
250 pF
C
L
=
250 pF
8 Outputs Switching
(Note 9)
8 Outputs Switching
(Note 8)
(Note 10)
Min
Max
Min
Max
Min
Max
t
PLH
Propagation Delay
1.5
6.0
2.0
8.0
2.5
10.5
ns
t
PHL
CPA or CPB to A
n
or B
n
1.5
6.0
2.0
8.0
2.5
10.5
t
PZH
Output Enable Time
1.5
6.0
2.0
8.0
2.5
11.5
ns
t
PZL
OEA or OEB to A
n
or B
n
1.5
6.0
2.0
8.0
2.5
11.5
t
PHZ
Output Disable Time
1.5
6.0
(Note 11)
(Note 11)
ns
t
PZL
OEA or OEB to A
n
or B
n
1.5
6.0
Symbol
Parameter
T
A
=
-
40
C to
+
85
C
T
A
=
-
40
C to
+
85
C
Units
V
CC
=
4.5V5.5V
V
CC
=
4.5V5.5V
C
L
=
50 pF
C
L
=
250 pF
8 Outputs Switching
8 Outputs Switching
(Note 12)
(Note 13)
Max
Max
t
OSHL
Pin to Pin Skew
1.0
1.5
ns
(Note 14)
HL Transitions
t
OSLH
Pin to Pin Skew
1.0
2.0
ns
(Note 14)
LH Transitions
t
PS
Duty Cycle
2.0
4.5
ns
(Note 15)
LHHL Skew
t
OST
Pin to Pin Skew
2.1
4.5
ns
(Note 14)
LH/HL Transitions
t
PV
Device to Device Skew
2.5
5.0
ns
(Note 16)
LH/HL Transitions
Symbol
Parameter
Typ
Units
Conditions
T
A
=
25
C
C
IN
Input Capacitance
5
pF
V
CC
=
0V (Non I/O Pins)
C
I/O
(Note 17)
Output Capacitance
11
pF
V
CC
=
5.0V (A
n
, B
n
)