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1999 Fairchild Semiconductor Corporation
DS011510
www.fairchildsemi.com
November 1992
Revised November 1999
7
4
AB
T3
74
Oct
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ip-
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3-
ST
A
T
E Output
s
74ABT374
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The ABT374 is an octal D-type flip-flop featuring separate
D-type inputs for each flip-flop and 3-STATE outputs for
bus-oriented applications. A buffered Clock (CP) and Out-
put Enable (OE) are common to all flip-flops.
Features
s
Edge-triggered D-type inputs
s
Buffered positive edge-triggered clock
s
3-STATE outputs for bus-oriented applications
s
Output sink capability of 64 mA, source capability of
32 mA
s
Guaranteed output skew
s
Guaranteed multiple output switching specifications
s
Output switching specified for both 50 pF and 250 pF
loads
s
Guaranteed simultaneous switching, noise level and
dynamic threshold performance
s
Guaranteed latchup protection
s
High impedance glitch free bus loading during entire
power up and power down cycle
s
Non-destructive hot insertion capability
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Pin Descriptions
Order Number
Package Number
Package Description
74ABT374CSC M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Body
74ABT374CSJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT374CMSA
MSA20
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74ABT374CMTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ABT374CPC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Pin Names
Description
D
0
D
7
Data Inputs
CP
Clock Pulse Input (Active Rising Edge)
OE
3-STATE Output Enable Input (Active LOW)
O
0
O
7
3-STATE Outputs
www.fairchildsemi.com
2
74ABT374
Functional Description
The ABT374 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE true outputs. The
buffered clock and buffered Output Enable are common to
all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold time
requirements on the LOW-to-HIGH Clock (CP) transition.
With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When OE is
HIGH, the outputs are in a high impedance state. Opera-
tion of the OE input does not affect the state of the flip-
flops.
Function Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
=
LOW-to-HIGH Transition
NC
=
No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs
Internal Outputs
Function
OE CP
D
Q
O
H
H
L
NC
Z
Hold
H
H
H
NC
Z
Hold
H
L
L
Z
Load
H
H
H
Z
Load
L
L
L
L
Data Available
L
H
H
H
Data Available
L
H
L
NC
NC
No Change in Data
L
H
H
NC
NC
No Change in Data
3
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74
A
B
T
3
7
4
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs
DC Electrical Characteristics
Note 3: For 8-bit toggling, I
CCD
<
0.8 mA/MHz.
Note 4: Guaranteed, but not tested.
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
55
C to
+
125
C
Junction Temperature under Bias
-
55
C to
+
150
C
V
CC
Pin Potential to
Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 2)
-
0.5V to
+
7.0V
Input Current (Note 2)
-
30 mA to
+
5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-Off
State
-
0.5V to 5.5V
in the HIGH State
-
0.5V to V
CC
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
DC Latchup Source Current:
OE Pin
-
150 mA
(Across Comm Operating Range)
Other Pins
-
500 mA
Over Voltage Latchup (I/O)
10V
Free Air Ambient Temperature
-
40
C to
+
85
C
Supply Voltage
+
4.5V to
+
5.5V
Minimum Input Edge Rate (
V/
t)
Data Input
50 mV/ns
Enable Input
20 mV/ns
Clock Input
100mV/ns
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
Min
I
IN
=
-
18 mA
V
OH
Output HIGH Voltage
2.5
V
Min
I
OH
=
-
3 mA
2.0
V
Min
I
OH
=
-
32 mA
V
OL
Output LOW Voltage
0.55
V
Min
I
OL
=
64 mA
I
IH
Input HIGH Current
1
A
Max
V
IN
=
2.7V (Note 4)
1
V
IN
=
V
CC
I
BVI
Input HIGH Current Breakdown Test
7
A
Max
V
IN
=
7.0V
I
IL
Input LOW Current
-
1
A
Max
V
IN
=
0.5V (Note 4)
-
1
V
IN
=
0.0V
V
ID
Input Leakage Test
4.75
V
0.0
I
ID
=
1.9
A, All Other Pins Grounded
I
OZH
Output Leakage Current
10
A
0
-
5.5V V
OUT
=
2.7V; OE
=
2.0V
I
OZL
Output Leakage Current
-
10
A
0
-
5.5V V
OUT
=
0.5V; OE
=
2.0V
I
OS
Output Short-Circuit Current
-
100
-
275
mA
Max
V
OUT
=
0.0V
I
CEX
Output High Leakage Current
50
A
Max
V
OUT
=
V
CC
I
ZZ
Bus Drainage Test
100
A
0.0
V
OUT
=
5.5V; All Others V
CC
or GND
I
CCH
Power Supply Current
50
A
Max
All Outputs HIGH
I
CCL
Power Supply Current
30
mA
Max
All Outputs LOW
I
CCZ
Power Supply Current
50
A
Max
OE
=
V
CC
; All Others at V
CC
or GND
I
CCT
Additional I
CC
/Input
Outputs Enabled
2.5
mA
V
I
=
V
CC
-
2.1V
Outputs 3-STATE
2.5
mA
Max
Enable Input V
I
=
V
CC
-
2.1V
Outputs 3-STATE
2.5
mA
Data Input V
I
=
V
CC
-
2.1V
All Others at V
CC
or GND
I
CCD
Dynamic I
CC
No Load
mA/
Max
Outputs OPEN
(Note 4)
0.30
MHz
OE
=
GND, (Note 3)
One Bit Toggling, 50% Duty Cycle
www.fairchildsemi.com
4
74ABT374
DC Electrical Characteristics
(SOIC package)
Note 5: Max number of outputs defined as (n). n
-
1 data inputs are driven 0V to 3V. One output at Low. Guaranteed, but not tested.
Note 6: Max number of outputs defined as (n). n
-
1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
Note 7: Max number of data inputs (n) switching. n
-
1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V
ILD
), 0V to threshold (V
IHD
).
Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and SSOP Package)
AC Operating Requirements
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
C
L
=
50 pF, R
L
=
500
V
OLP
Quiet Output Maximum Dynamic V
OL
0.5
0.8
V
5.0
T
A
=
25
C (Note 5)
V
OLV
Quiet Output Minimum Dynamic V
OL
-
1.3
-
0.9
V
5.0
T
A
=
25
C (Note 5)
V
OHV
Minimum HIGH Level Dynamic Output Voltage
2.5
3.0
V
5.0
T
A
=
25
C (Note 6)
V
IHD
Minimum HIGH Level Dynamic Input Voltage
2.0
1.6
V
5.0
T
A
=
25
C (Note 7)
V
ILD
Maximum LOW Level Dynamic Input Voltage
1.3
0.8
V
5.0
T
A
=
25
C (Note 7)
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
55
C to
+
125
C
T
A
=
-
40
C to
+
85
C
Units
V
CC
=
+
5.0V
V
CC
=
4.5V to 5.5V
V
CC
=
4.5V to 5.5V
C
L
=
50 pF
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
Min
Max
f
MAX
Maximum Clock Frequency
150
200
150
150
MHz
t
PLH
Propagation Delay
2.0
3.2
5.0
1.4
6.6
2.0
5.0
ns
t
PHL
CP to O
n
2.0
3.3
5.0
2.0
7.6
2.0
5.0
t
PZH
Output Enable Time
1.5
3.1
5.3
0.8
5.7
1.5
5.3
ns
t
PZL
1.5
3.1
5.3
1.5
7.2
1.5
5.3
t
PHZ
Output Disable Time
1.5
3.6
5.4
1.3
7.2
1.5
5.4
ns
t
PLZ
1.5
3.4
5.4
1.0
7.0
1.5
5.4
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
55
C to
+
125
C
T
A
=
-
40
C to
+
85
C
Units
V
CC
=
+
5.0V
V
CC
=
4.5V to 5.5V
V
CC
=
4.5V to 5.5V
C
L
=
50 pF
C
L
=
50 pF
C
L
=
50 pF
Min
Max
Min
Max
Min
Max
t
S
(H)
Setup Time, HIGH
1.5
2.5
1.0
ns
t
S
(L)
or LOW D
n
to CP
1.5
2.5
1.5
t
H
(H)
Hold Time, HIGH
1.0
2.5
1.0
ns
t
H
(L)
or LOW D
n
to CP
1.0
2.5
1.0
t
W
(H)
Pulse Width, CP
3.0
3.3
3.0
ns
t
W
(L)
HIGH or LOW
3.0
3.3
3.0
5
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74
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7
4
Extended AC Electrical Characteristics
(SOIC Package)
Note 8: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 9: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac-
itors in the standard AC load. This specification pertains to single output switching only.
Note 10: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 11: The 3-STATE delay Time is dominated by the RC network (500
, 250 pF) on the output and has been excluded from the datasheet.
Skew
(Note 16)
(SOIC Package)
Note 12: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 13: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (t
OSHL
), LOW-to-HIGH (t
OSLH
), or any combination switching LOW-to-HIGH and/or HIGH-
to-LOW (t
OST
). This specification is guaranteed but not tested.
Note 15: Propagation delay variation for a given set of conditions (i.e., temperature and V
CC
) from device to device. This specification is guaranteed but not
tested.
Note 16: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Capacitance
Note 17: C
OUT
is measured at frequency f
=
1 MHz, per MIL-STD-883, Method 3012.
Symbol
Parameter
T
A
=
-
40
C to
+
85
C
T
A
=
-
40
C to
+
85
C
T
A
=
-
40
C to
+
85
C
Units
V
CC
=
4.5V to 5.5V
V
CC
=
4.5V to 5.5V
V
CC
=
4.5V to 5.5V
C
L
=
50 pF
C
L
=
250 pF
C
L
=
250 pF
8 Outputs Switching
(Note 9)
8 Outputs Switching
(Note 8)
(Note 10)
Min
Max
Min
Max
Min
Max
t
PLH
Propagation Delay
1.5
5.7
2.0
7.8
2.0
10.0
ns
t
PHL
CP to O
n
1.5
5.7
2.0
7.8
2.0
10.0
t
PZH
Output Enable Time
1.5
6.2
2.0
8.0
2.0
10.5
ns
t
PZL
1.5
6.2
2.0
8.0
2.0
10.5
t
PHZ
Output Disable Time
1.0
5.5
(Note 11)
(Note 11)
ns
t
PZL
1.0
5.5
Symbol
Parameter
T
A
=
-
40
C to
+
85
C
T
A
=
-
40
C to
+
85
C
Units
V
CC
=
4.5V5.5V
V
CC
=
4.5V5.5V
C
L
=
50 pF
C
L
=
250 pF
8 Outputs Switching
8 Outputs Switching
(Note 12)
(Note 13)
Max
Max
t
OSHL
Pin to Pin Skew
1.0
1.8
ns
(Note 14)
HL Transitions
t
OSLH
Pin to Pin Skew
1.0
1.8
ns
(Note 14)
LH Transitions
t
PS
Duty Cycle
1.8
4.3
ns
(Note 13)
LHHL Skew
t
OST
Pin to Pin Skew
2.0
4.3
ns
(Note 14)
LH/HL Transitions
t
PV
Device to Device Skew
2.5
4.6
ns
(Note 15)
LH/HL Transitions
Symbol
Parameter
Typ
Units
Conditions
(T
A
=
25
C)
C
IN
Input Capacitance
5.0
pF
V
CC
=
0V
C
OUT
(Note 17)
Output Capacitance
9.0
pF
V
CC
=
5.0V