1999 Fairchild Semiconductor Corporation
DS500294
www.fairchildsemi.com
August 1999
Revised October 1999
7
4
AC
T1
8823
1
8
-Bi
t
D-T
ype Fli
p
-F
lop wit
h
3-
ST
A
T
E Output
s
74ACT18823
18-Bit D-Type Flip-Flop with 3-STATE Outputs
General Description
The ACT18823 contains eighteen non-inverting D-type flip-
flops with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. A buffered clock
(CP), Clear (CLR), Clock Enable (EN) and Output Enable
(OE) are common to each byte and can be shorted
together for full 18-bit operation.
Features
s
Broadside pinout allows for easy board layout
s
Separate control logic for each byte
s
Extra data width for wider address/data paths or buses
carrying parity
s
Outputs source/sink 24 mA
s
TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagram
FACT
TM
is a trademark of Fairchild Semiconductor Corporation.
Order Number
Package Number
Package Description
74ACT18823SSC
MS56A
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74ACT18823MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names
Description
OE
n
Output Enable Input (Active LOW)
CLR
n
Clear (Active LOW)
EN
n
Clock Enable (Active LOW)
CP
n
Clock Pulse Input
I
0
I
17
Inputs
O
0
O
17
Outputs
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2
74ACT18823
Functional Description
The ACT18823 consists of eighteen D-type edge-triggered
flip-flops. These have 3-STATE outputs for bus systems
organized with inputs and outputs on opposite sides. The
device is byte controlled with each byte functioning identi-
cally, but independent of the other. The control pins can be
shorted together to obtain full 16-bit operation. The follow-
ing description applies to each byte. The buffered clock
(CP
n
) and buffered Output Enable (OE
n
) are common to all
flip-flops within that byte. The flip-flops will store the state
of their individual D inputs that meet set-up and hold time
requirements on the LOW-to-HIGH CP
n
transition. With
OE
n
LOW, the contents of the flip-flops are available at the
outputs. When OE
n
is HIGH, the outputs go to the imped-
ance state. Operation of the OE
n
input does not affect the
state of the flip-flops. In addition to the Clock and Output
Enable pins, there are Clear (CLR
n
) and Clock Enable
(EN
n
) pins. These devices are ideal for parity bus interfac-
ing in high performance systems.
When CLR
n
is LOW and OE
n
is LOW, the outputs are
LOW. When CLR
n
is HIGH, data can be entered into the
flip-flops. When EN
n
is LOW, data on the inputs is trans-
ferred to the outputs on the LOW-to-HIGH clock transition.
When the EN
n
is HIGH, the outputs do not change state,
regardless of the data or clock input transitions.
Function Table
(Note 1)
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
=
LOW-to-HIGH Transition
NC
=
No Change
Note 1: The table represents the logic for one byte. The two bytes are inde-
pendent of each other and function identically.
Logic Diagrams
Byte 1 (0:8)
Byte 2 (9:17)
Inputs
Internal Output
Function
OE
CLR
EN
CP
I
n
Q
O
n
H
X
L
L
L
Z
High Z
H
X
L
H
H
Z
High Z
H
L
X
X
X
L
Z
Clear
L
L
X
X
X
L
L
Clear
H
H
H
X
X
NC
Z
Hold
L
H
H
X
X
NC
NC
Hold
H
H
L
L
L
Z
Load
H
H
L
H
H
Z
Load
L
H
L
L
L
L
Load
L
H
L
H
H
H
Load
3
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4
AC
T1
8823
Absolute Maximum Ratings
(Note 2)
Recommended Operating
Conditions
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT
TM
circuits outside databook specifications.
DC Electrical Characteristics
Note 3: All outputs loaded; thresholds associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Supply Voltage (V
CC
)
-
0.5V to
+
7.0V
DC Input Diode Current (I
IK
)
V
I
=
-
0.5V
-
20 mA
V
I
=
V
CC
+
0.5V
+
20 mA
DC Output Diode Current (I
OK
)
V
O
=
-
0.5V
-
20 mA
V
O
=
V
CC
+
0.5V
+
20 mA
DC Output Voltage (V
O
)
-
0.5V to V
CC
+
0.5V
DC Output Source/Sink Current (I
O
)
50 mA
DC V
CC
or Ground Current
Per Output Pin
50 mA
Junction Temperature
PDIP/SOIC
+
140
C
Storage Temperature
-
65
C to
+
150
C
Supply Voltage (V
CC
)
4.5V to 5.5V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
-
40
C to
+
85
C
Minimum Input Edge Rate (
V/
t)
125 mV/ns
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
Symbol
Parameter
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
(V)
Typ
Guaranteed Limits
V
IH
Minimum HIGH
4.5
1.5
2.0
2.0
V
V
OUT
=
0.1V
Input Voltage
5.5
1.5
2.0
2.0
or V
CC
-
0.1V
V
IL
Maximum LOW
4.5
1.5
0.8
0.8
V
V
OUT
=
0.1V
Input Voltage
5.5
1.5
0.8
0.8
or V
CC
-
0.1V
V
OH
Minimum HIGH
4.5
4.49
4.4
4.4
V
I
OUT
=
-
50
A
Output Voltage
5.5
5.49
5.4
5.4
V
IN
=
V
IL
or V
IH
4.5
3.86
3.76
V
I
OH
=
-
24 mA
5.5
4.86
4.76
I
OH
=
-
24 mA (Note 3)
V
OL
Maximum LOW
4.5
0.001
0.1
0.1
V
I
OUT
=
50
A
Output Voltage
5.5
0.001
0.1
0.1
V
IN
=
V
IL
or V
IH
4.5
0.36
0.44
V
I
OL
=
24 mA
5.5
0.36
0.44
I
OL
=
24 mA (Note 3)
I
OZ
Maximum 3-STATE
5.5
0.5
5.0
A
V
I
=
V
IL
, V
IH
Leakage Current
V
O
=
V
CC
, GND
I
IN
Maximum Input Leakage Current
5.5
0.1
1.0
A
V
I
=
V
CC
, GND
I
CCT
Maximum I
CC
/Input
5.5
0.6
1.5
mA
V
I
=
V
CC
-
2.1V
I
CC
Maximum Quiescent Supply Current
5.5
8.0
80.0
A
V
IN
=
V
CC
or GND
I
OLD
Minimum Dynamic
5.5
75
mA
V
OLD
=
1.65V Max
I
OHD
Output Current (Note 4)
-
75
mA
V
OHD
=
3.85V Min
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4
74ACT18823
AC Electrical Characteristics
Note 5: Voltage Range 5.0 is 5.0V
0.5V.
AC Operating Requirements
Note 6: Voltage Range 5.0 is 5.0V
0.5V.
Capacitance
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Symbol
Parameter
(V)
C
L
=
50 pF
C
L
=
50 pF
Units
(Note 5)
Min
Max
Min
Max
f
MAX
Maximum Clock
5.0
100
90
MHz
Frequency
t
PHL
Propagation Delay
5.0
2.0
9.0
2.0
9.5
ns
t
PLH
CP
n
to O
n
2.0
9.0
2.0
9.5
t
PHL
Propagation Delay
5.0
2.0
9.0
2.0
9.5
ns
CLR
n
to O
n
t
PZL
Output Enable Time
5.0
2.0
9.0
2.0
10.0
ns
t
PZH
2.0
9.0
2.0
10.0
t
PLZ
Output Disable Time
5.0
1.5
7.0
1.5
7.5
ns
t
PHZ
1.5
8.0
1.5
8.5
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Symbol
Parameter
(V)
C
L
=
50 pF
C
L
=
50 pF
Units
(Note 6)
Guaranteed Minimum
t
S
Setup Time, HIGH or LOW,
5.0
3.0
3.0
ns
Input to Clock
t
H
Hold Time, HIGH or LOW,
5.0
1.5
1.5
ns
Input to Clock
t
S
Setup Time, HIGH or LOW,
5.0
3.0
3.0
ns
Enable to Clock
t
H
Hold Time, HIGH or LOW,
5.0
1.5
1.5
ns
Enable to Clock
t
W
CP
n
Pulse Width,
5.0
4.0
4.0
ns
HIGH or LOW
t
W
CLR
n
Pulse Width,
5.0
4.0
4.0
ns
HIGH or LOW
t
rec
Recovery Time,
5.0
6.0
6.0
ns
CLR
n
to CP
n
Symbol
Parameter
Typ
Units
Conditions
C
IN
Input Pin Capacitance
4.5
pF
V
CC
=
5.0V
C
PD
Power Dissipation Capacitance
95
pF
V
CC
=
5.0V
5
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4
AC
T1
8823
Physical Dimensions
inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS56A
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6
74ACT188
23 18-
Bit
D-
T
ype F
l
i
p
-Fl
op wi
th
3-
S
T
A
T
E
O
u
t
puts
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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