2001 Fairchild Semiconductor Corporation
DS010934
www.fairchildsemi.com
June 1991
Revised April 2001
7
4
AC
TQ163
73 16-
Bit
T
r
anspar
ent
Lat
c
h wi
th
3-ST
A
T
E Out
puts
74ACTQ16373
16-Bit Transparent Latch with 3-STATE Outputs
General Description
The ACTQ16373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear transparent to the data when the Latch Enable (LE)
is HIGH. When LE is low, the data that meets the setup
time is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
high Z state. The ACTQ16373 utilizes Fairchild's Quiet
Series
technology to guarantee quiet output switching
and improved dynamic threshold performance. FACT Quiet
Series
features GTO
output control for superior perfor-
mance.
Features
s
Utilizes Fairchild FACT Quiet Series technology
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin output skew
s
Separate control logic for each byte
s
16-bit version of the ACTQ373
s
Outputs source/sink 24 mA
s
Additional specs for Multiple Output Switching
s
Output Loading specs for both 50 pF and 250 pF loads
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagram
FACT
, Quiet Series
, FACT Quiet Series
, and GTO
are trademarks of Fairchild Semiconductor Corporation.
Order Number
Package Number
Package Description
74ACTQ16373SSC
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
74ACTQ16373MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names
Description
OE
n
Output Enable Input (Active LOW)
LE
n
Latch Enable Input
I
0
I
15
Inputs
O
0
O
15
Outputs
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2
74ACTQ16373
Functional Description
The ACTQ16373 contains sixteen D-type latches with 3-
STATE standard outputs. The device is byte controlled with
each byte functioning identically, but independent of the
other. Control pins can be shorted together to obtain full
16-bit operation. The following description applies to each
byte. When the Latch Enable (LE
n
) input is HIGH, data on
the D
n
enters the latches. In this condition the latches are
transparent, i.e., a latch output will change states each time
its D input changes. When LE
n
is LOW, the latches store
information that was present on the D inputs a setup time
preceding the HIGH-to-LOW transition of LE
n
. The 3-
STATE standard outputs are controlled by the Output
Enable (OE
n
) input. When OE
n
is LOW, the standard out-
puts are in the 2-state mode. When OE
n
is HIGH, the stan-
dard outputs are in the high impedance mode but this does
not interfere with entering new data into the latches.
Truth Tables
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
Previous
=
previous output prior to HIGH-to-LOW transition of LE
Logic Diagrams
Inputs
Outputs
LE
1
OE
1
I
0
I
7
O
0
O
7
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
(Previous)
Inputs
Outputs
LE
2
OE
2
I
8
I
15
O
8
O
15
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
(Previous)
3
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7
4
AC
TQ163
73
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are those values beyond which dam-
age to the device may occur. The databook specifications should be met,
without exception to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT
circuits outside databook specifications.
DC Electrical Characteristics
Note 2: All outputs loaded; thresholds associated with output under test.
Note 3: Maximum test duration 2.0 ms; one output loaded at a time.
Note 4: Worst case package
Note 5: Maximum number of outputs that can switch simultaneously is n. (n
-
1) outputs are switched LOW and one output held LOW.
Note 6: Maximum number of outputs that can switch simultaneously is n. (n
-
1) outputs are switched HIGH and one output held HIGH.
Note 7: Max number of data inputs (n) switching, (n
-
1) input switching 0V to 3V. Input under test switching 3V to threshold (V
ILD
)
Supply Voltage (V
CC
)
-
0.5V to
+
7.0V
DC Input Diode Current (I
IK
)
V
I
=
-
0.5V
-
20 mA
V
I
=
V
CC
+
0.5V
+
20 mA
DC Output Diode Current (I
OK
)
V
O
=
-
0.5V
-
20 mA
V
O
=
V
CC
+
0.5V
+
20 mA
DC Output Voltage (V
O
)
-
0.5V to V
CC
+
0.5V
DC Output Source/Sink Current (I
O
)
+
50 mA
DC V
CC
or Ground Current
+
50 mA
per Output Pin
Junction Temperature
+
140
C
Storage Temperature
-
65
C to
+
150
C
Supply Voltage (V
CC
)
4.5V to 5.5V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
-
40
C to
+
85
C
Minimum Input Edge Rate (
V/
t)
125 mV/ns
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
Symbol
Parameter
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
(V)
Typ
Guaranteed Limits
V
IH
Minimum HIGH
4.5
1.5
2.0
2.0
V
V
OUT
=
0.1V
Input Voltage
5.5
1.5
2.0
2.0
or V
CC
-
0.1V
V
IL
Maximum LOW
4.5
1.5
0.8
0.8
V
V
OUT
=
0.1V
Input Voltage
5.5
1.5
0.8
0.8
or V
CC
-
0.1V
V
OH
Minimum HIGH
4.5
4.49
4.4
4.4
V
I
OUT
=
-
50
A
Output Voltage
5.5
5.49
5.4
5.4
V
IN
=
V
IL
or V
IH
4.5
3.86
3.76
V
I
OH
=
-
24 mA
5.5
4.86
4.76
I
OH
=
-
24 mA (Note 2)
V
OL
Maximum LOW
4.5
0.001
0.1
0.1
V
I
OUT
=
50
A
Output Voltage
5.5
0.001
0.1
0.1
V
IN
=
V
IL
or V
IH
4.5
0.36
0.44
V
I
OL
=
24 mA
5.5
0.36
0.44
I
OL
=
24 mA (Note 2)
I
OZ
Maximum 3-STATE
5.5
0.5
5.0
A
V
I
=
V
IL
, V
IH
Leakage Current
V
O
=
V
CC
, GND
I
IN
Maximum Input Leakage Current
5.5
0.1
1.0
A
V
I
=
V
CC
, GND
I
CCT
Maximum I
CC
/Input
5.5
0.6
1.5
mA
V
I
=
V
CC
-
2.1V
I
CC
Max Quiescent Supply Current
5.5
8.0
80.0
A
V
IN
=
V
CC
or GND
I
OLD
Minimum Dynamic
5.5
75
mA
V
OLD
=
1.65V Max
I
OHD
Output Current (Note 3)
-
75
mA
V
OHD
=
3.85V Min
V
OLP
Quiet Output
5.0
0.5
0.8
V
Figures 1, 2
Maximum Dynamic V
OL
(Note 5)(Note 6)
V
OLV
Quiet Output
5.0
-
0.5
-
1.0
V
Figures 1, 2
Minimum Dynamic V
OL
(Note 5)(Note 6)
V
OHP
Maximum Overshoot
5.0
V
OH
+
1.0 V
OH
+
1.5
V
Figures 1, 2
(Note 4)(Note 6)
V
OHV
Minimum V
CC
Droop
5.0
V
OH
-
1.0 V
OH
-
1.8
V
Figures 1, 2
(Note 4)(Note 6)
V
IHD
Minimum HIGH Dynamic Input Voltage Level
5.0
1.7
2.0
V
(Note 4)(Note 7)
V
ILD
Maximum LOW Dynamic Input Voltage Level
5.0
1.2
0.8
V
(Note 4)(Note 7)
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4
74ACTQ16373
AC Electrical Characteristics
Note 8: Voltage Range 5.0 is 5.0V
0.5V.
Extended AC Electrical Characteristics
Note 9: Voltage Range 5.0 is 5.0V
0.5V.
Note 10: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 11: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 12: 3-STATE delays are load dominated and have been excluded from the datasheet.
Note 13: The Output Disable Time is dominated by the RC Network (500
, 250 pF) on the output and has been excluded from the datasheet.
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (t
OSHL
), LOW-to-HIGH (t
OSLH
), or any combination switching LOW-to-HIGH and/or HIGH-
to-LOW (t
OST
).
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Symbol
Parameter
(V)
C
L
=
50 pF
C
L
=
50 pF
Units
(Note 8)
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay
5.0
3.1
5.3
7.9
3.1
8.4
ns
t
PHL
D
n
to O
n
2.6
4.6
7.3
2.6
7.8
t
PLH
Propagation Delay
5.0
3.1
5.4
7.9
3.2
8.4
ns
t
PHL
LE to O
n
2.8
4.9
7.3
2.8
7.8
t
PZH
Output Enable
5.0
2.5
4.7
7.4
2.5
7.9
ns
t
PZL
Delay
2.7
4.8
7.5
2.7
8.0
t
PHZ
Output Disable
5.0
2.1
5.1
7.9
2.1
8.2
ns
t
PLZ
Delay
2.0
4.5
7.4
2.0
7.9
T
A
=
-
40
C to
+
85
C
T
A
=
-
40
C to
+
85
C
V
CC
C
L
=
50 pF
C
L
=
250 pF
Symbol
Parameter
(V)
16 Outputs Switching
(Note 11)
Units
(Note 9)
(Note 10)
Min
Max
Min
Max
t
PLH
Propagation Delay
5.0V
4.7
12.7
6.6
15.7
ns
t
PHL
Data to Output
4.6
10.6
6.4
14.5
t
PLH
Propagation Delay
5.0V
4.6
13.3
6.3
15.3
ns
t
PHL
Latch Enable to Output
4.1
10.4
5.8
13.6
t
PZH
Output Enable
5.0V
3.5
10.4
(Note 12)
ns
t
PZL
Time
3.6
10.9
t
PHZ
Output Disable
5.0V
3.4
8.5
(Note 13)
ns
t
PLZ
Time
3.1
8.1
t
OSHL
Pin-to-Pin Skew
5.0V
1.3
ns
(Note 14)
HL Data to Output
t
OSLH
Pin-to-Pin Skew
5.0V
2.1
ns
(Note 14)
LH Data to Output
t
OST
Pin-to-Pin Skew
5.0V
4.0
ns
(Note 14)
LH/HL Data to Output
5
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7
4
AC
TQ163
73
AC Operating Requirements
Note 15: Voltage Range 5.0 is 5.0V
0.5V
Capacitance
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Units
Symbol
Parameter
(V)
C
L
=
50 pF
C
L
=
50 pF
(Note 15)
Guaranteed Minimum
t
S
Setup Time, HIGH or LOW,
5.0
3.0
3.0
ns
Input to Clock
t
H
Hold Time, HIGH or LOW
5.0
1.5
1.5
ns
Input to Clock
t
W
CS Pulse Width,
5.0
4.0
4.0
ns
HIGH or LOW
Symbol
Parameter
Typ
Units
Conditions
C
IN
Input Capacitance
4.5
pF
V
CC
=
5.0V
C
PD
Power Dissipation Capacitance
30
pF
V
CC
=
5.0V
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