2000 Fairchild Semiconductor Corporation
DS010635
www.fairchildsemi.com
January 1990
Revised September 2000
7
4
AC
Q646 74AC
T
Q
6
4
6
Qui
e
t Seri
es
Oct
a
l T
r
a
n
sceiv
e
r/
R
e
gist
er wit
h
3-
ST
A
T
E Output
s
74ACQ646 74ACTQ646
Quiet Series
Octal Transceiver/Register
with 3-STATE Outputs
General Description
The ACQ/ACTQ646 consist of registered bus transceiver
circuits, with outputs, D-type flip-flops, and control circuitry
providing multiplexed transmission of data directly from the
input bus or from the internal storage registers. Data on the
A or B bus will be loaded into the respective registers on
the LOW-to-HIGH transition of the appropriate clock pin
(CPAB or CPBA). The four fundamental handling functions
available are illustrated in Figure 1, Figure 2, Figure 3 and
Figure 4.
The ACQ/ACTQ utilizes Fairchild Quiet Series
technol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series
fea-
tures GTO
output control and undershoot corrector in
addition to a split ground bus for superior performance.
Features
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin skew AC performance
s
Independent registers for A and B busses
s
Multiplexed real-time and stored data transfers
s
300 mil slim dual-in-line package
s
Outputs source/sink 24 mA
s
Faster prop delays than the standard AC/ACT646
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Pin Descriptions
FACT
, Quiet Series
, FACT Quiet Series
and GTO
are trademarks of Fairchild Semiconductor Corporation
Order Number
Package Number
Package Description
74ACQ646SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACQ464ASPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74ACTQ646SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACTQ464ASPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names
Descriptions
A
0
A
7
Data Register A Inputs
Data Register A Outputs
B
0
B
7
Data Register B Inputs
Data Register B Outputs
CPAB, CPBA
Clock Pulse Inputs
SAB, SBA
Transmit/Receive Inputs
G
Output Enable Input
DIR
Direction Control Input
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74
A
C
Q646
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AC
T
Q
646
Logic Symbols
IEEE/IEC
Function Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Transition
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled; i.e., data
at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.
Inputs
Data I/O (Note 1)
Function
G
DIR
CPAB CPBA
SAB
SBA
A
0
A
7
B
0
B
7
H
X
H or L H or L
X
X
Isolation
H
X
X
X
X
Input
Input
Clock A
n
Data into A Register
H
X
X
X
X
Clock B
n
Data into B Register
L
H
X
X
L
X
A
n
to B
n
--Real Time (Transparent Mode)
L
H
X
L
X
Input
Output Clock A
n
Data into A Register
L
H
H or L
X
H
X
A Register to B
n
(Stored Mode)
L
H
X
H
X
Clock A
n
Data into A Register and Output to B
n
L
L
X
X
X
L
B
n
to A
n
--Real Time (Transparent Mode)
L
L
X
X
L
Output
Input
Clock B
n
Data into B Register
L
L
X
H or L
X
H
B Register to A
n
(Stored Mode)
L
L
X
X
H
Clock B
n
Data into B Register and Output to A
n
3
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7
4
AC
Q646
74AC
T
Q
6
4
6
Real Time Transfer
A-Bus to B-Bus
FIGURE 1.
Real Time Transfer
B-Bus to A-Bus
FIGURE 2.
Storage from
Bus to Register
FIGURE 3.
Transfer from
Register to Bus
FIGURE 4.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74
A
C
Q646
7
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AC
T
Q
646
Absolute Maximum Ratings
(Note 2)
Recommended Operating
Conditions
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT
circuits outside databook specifications.
DC Electrical Characteristics for ACQ
Supply Voltage (V
CC
)
-
0.5V to
+
7.0V
DC Input Diode Current (I
IK
)
V
I
=
-
0.5V
-
20 mA
V
I
=
V
CC
+
0.5V
+
20 mA
DC Input Voltage (V
I
)
-
0.5V to V
CC
+
0.5V
DC Output Diode Current (I
OK
)
V
O
=
-
0.5V
-
20 mA
V
O
=
V
CC
+
0.5V
+
20 mA
DC Output Voltage (V
O
)
-
0.5V to V
CC
+
0.5V
DC Output Source
or Sink Current (I
O
)
50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
50 mA
Storage Temperature (T
STG
)
-
65
C to
+
150
C
DC Latch-Up Source
or Sink Current
300 mA
Junction Temperature (T
J
)
PDIP
140
C
Supply Voltage (V
CC
)
ACQ
2.0V to 6.0V
ACTQ
4.5V to 5.5V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
-
40
C to
+
85
C
Minimum Input Edge Rate
V/
t
ACQ Devices
V
IN
from 30% to 70% of V
CC
V
CC
@ 3.0V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate
V/
t
ACTQ Devices
V
IN
from 0.8V to 2.0V
V
CC
@ 4.5V, 5.5V
125 mV/ns
Symbol
Parameter
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
(V)
Typ
Guaranteed Limits
V
IH
Minimum HIGH Level
3.0
1.5
2.1
2.1
V
OUT
=
0.1V
Input Voltage
4.5
2.25
3.15
3.15
V
or V
CC
-
0.1V
5.5
2.75
3.85
3.85
V
IL
Maximum LOW Level
3.0
1.5
0.9
0.9
V
OUT
=
0.1V
Input Voltage
4.5
2.25
1.35
1.35
V
or V
CC
-
0.1V
5.5
2.75
1.65
1.65
V
OH
Minimum HIGH Level
3.0
2.99
2.9
2.9
Output Voltage
4.5
4.49
4.4
4.4
V
I
OUT
=
-
50
A
5.5
5.49
5.4
5.4
V
IN
=
V
IL
or V
IH
3.0
2.56
2.46
I
OH
=
-
12 mA
4.5
3.86
3.76
V
I
OH
=
-
24 mA
5.5
4.85
4.76
I
OH
=
-
24 mA (Note 3)
V
OL
Maximum LOW Level
3.0
0.002
0.1
0.1
Output Voltage
4.5
0.001
0.1
0.1
V
I
OUT
=
50
A
5.5
0.001
0.1
0.1
V
IN
=
V
IL
or V
IH
3.0
0.36
0.44
I
OL
=
12 mA
4.5
0.36
0.44
V
I
OL
=
24 mA
5.5
0.36
0.44
I
OL
=
24 mA (Note 3)
I
IN
(Note 5) Maximum Input Leakage Current
5.5
0.1
1.0
A
V
I
=
V
CC
, GND
I
OLD
Minimum Dynamic
5.5
75
mA
V
OLD
=
1.65V Max
I
OHD
Output Current (Note 4)
5.5
-
75
mA
V
OHD
=
3.85V Min
I
CC
Maximum Quiescent
5.5
8.0
80.0
A
V
IN
=
V
CC
or GND
(Note 5)
Supply Current
I
OZT
Maximum I/O
V
I
(OE)
=
V
IL
, V
IH
Leakage Current
5.5
0.6
6.0
A
V
I
=
V
CC
, GND
(A
n
, B
n
Inputs)
V
O
=
V
CC
, GND
V
OLP
Quiet Output
5.0
1.1
1.5
V
Figures 5, 6
Maximum Dynamic V
OL
(Note 6)(Note 7)
5
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AC
Q646
74AC
T
Q
6
4
6
DC Electrical Characteristics for ACQ
(Continued)
Note 3: Maximum of 8 outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
Note 6: Plastic DIP package.
Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 5V. One output @ GND.
Note 8: Max number of Data Inputs (n) switching. (n
-
1) inputs switching 0V to 5V (ACQ). Input-under-test switching 5V to threshold (V
ILD
),
0V to threshold (V
IHD
) f
=
1 MHz.
DC Electrical Characteristics for ACTQ
Note 9: All outputs loaded; thresholds on input associated with output under test.
Note 10: Maximum test duration 2.0 ms, one output loaded at a time.
Note 11: Plastic DIP Package.
Note 12: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND.
Note 13: Max number of data inputs (n) switching. (n
-
1) inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (V
ILD
),
0V to threshold (V
IHD
), f
=
1 MHz.
Symbol
Parameter
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
(V)
Typ
Guaranteed Limits
V
OLV
Quiet Output
5.0
-
0.6
-
1.2
V
Figures 5, 6
Minimum Dynamic V
OL
(Note 6)(Note 7)
V
IHD
Minimum HIGH Level
5.0
3.1
3.5
V
(Note 6)(Note 8)
Dynamic Input Voltage
V
ILD
Maximum LOW Level
5.0
1.9
1.5
V
(Note 6)(Note 8)
Dynamic Input Voltage
Symbol
Parameter
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
(V)
Typ
Guaranteed Limits
V
IH
Minimum HIGH Level
4.5
1.5
2.0
2.0
V
V
OUT
=
0.1V
Input Voltage
5.5
1.5
2.0
2.0
or V
CC
-
0.1V
V
IL
Maximum LOW Level
4.5
1.5
0.8
0.8
V
V
OUT
=
0.1V
Input Voltage
5.5
1.5
0.8
0.8
or V
CC
-
0.1V
V
OH
Minimum HIGH Level
4.5
4.49
4.4
4.4
V
I
OUT
=
-
50
A
Output Voltage
5.5
5.49
5.4
5.4
V
IN
=
V
IL
or V
IH
4.5
3.86
3.76
V
I
OH
=
-
24 mA
5.5
4.86
4.76
I
OH
=
-
24 mA (Note 9)
V
OL
Maximum LOW Level
4.5
0.001
0.1
0.1
V
I
OUT
=
50
A
Output Voltage
5.5
0.001
0.1
0.1
V
IN
=
V
IL
or V
IH
4.5
0.36
0.44
V
I
OL
=
24 mA
5.5
0.36
0.44
I
OL
=
24 mA (Note 9)
I
IN
Maximum Input Leakage Current
5.5
0.1
1.0
A
V
I
=
V
CC
, GND
I
OZT
Maximum I/O Leakage Current
5.5
0.6
6.0
A
V
I
=
V
IL
, V
IH
(A
n
, B
n
Inputs)
V
O
=
V
CC
, GND
I
CCT
Maximum I
CC
/Input
5.5
0.6
1.5
mA
V
I
=
V
CC
-
2.1V
I
OLD
Minimum Dynamic
5.5
75
mA
V
OLD
=
1.65V Max
I
OHD
Output Current (Note 10)
5.5
-
75
mA
V
OHD
=
3.85V Min
I
CC
Maximum Quiescent
5.5
8.0
80.0
A
V
IN
=
V
CC
Supply Current
or GND
V
OLP
Quiet Output
5.0
1.1
1.5
V
Figures 5, 6
Maximum Dynamic V
OL
(Note 11)(Note 12)
V
OLV
Quiet Output
5.0
-
0.6
-
1.2
V
Figures 5, 6
Minimum Dynamic V
OL
(Note 11)(Note 12)
V
IHD
Minimum HIGH Level
5.0
1.7
2.0
V
(Note 11)(Note 13)
Dynamic Input Voltage
V
ILD
Maximum LOW Level
5.0
1.2
0.8
V
(Note 11)(Note 13)
Dynamic Input Voltage
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A
C
Q646
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AC
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Q
646
AC Electrical Characteristics for ACQ
Note 14: Voltage Range 3.3 is 3.3V
0.3V.
Voltage Range 5.0 is 5.0V
0.5V
Note 15: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device.
The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by
design. Not tested.
AC Operating Requirements for ACQ
Note 16: Voltage Range 5.0 is 5.0V
0.5V
Voltage Range 3.3 is 3.3V
0.3V
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Symbol
Parameter
(V)
C
L
=
50 pF
C
L
=
50 pF
Units
(Note 14)
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay
3.3
3.5
9.0
12.0
3.5
13.0
ns
Bus to Bus
5.0
2.5
6.5
9.0
2.5
9.5
t
PHL
Propagation Delay
3.3
3.5
9.0
12.0
3.5
13.0
ns
Bus to Bus
5.0
2.5
6.5
9.0
2.5
9.5
t
PLH
Propagation Delay
3.3
3.5
10.0
13.0
3.5
14.0
ns
Clock to Bus
5.0
2.5
7.0
9.5
2.5
10.5
t
PHL
Propagation Delay
3.3
3.5
10.0
13.0
3.5
14.0
ns
Clock to Bus
5.0
2.5
7.0
9.5
2.5
10.5
t
PLH
Propagation Delay
3.3
3.5
9.5
12.5
3.5
13.5
SBA or SAB to A
n
or B
n
5.0
2.5
6.5
9.0
2.5
10.0
ns
(w/A
n
or B
n
HIGH or LOW)
t
PHL
Propagation Delay
3.3
3.5
9.5
12.5
3.5
13.5
SBA or SAB to A
n
or B
n
5.0
2.5
6.5
9.0
2.5
10.0
ns
(w/A
n
or B
n
HIGH or LOW)
t
PZH
Enable Time
3.3
3.5
10.5
14.5
3.5
15.5
ns
G to A
n
or B
n
5.0
2.5
8.0
10.5
2.5
11.5
t
PZL
Enable Time
3.3
3.5
10.5
14.5
3.5
15.5
ns
G to A
n
or B
n
5.0
2.5
8.0
10.5
2.5
11.5
t
PHZ
Disable Time
3.3
2.5
8.0
11.0
2.5
12.0
ns
G to A
n
or B
n
5.0
1.5
5.0
7.5
1.5
8.0
t
PLZ
Disable Time
3.3
2.5
8.0
11.0
2.5
12.0
ns
G to A
n
or B
n
5.0
1.5
5.0
7.5
1.5
8.0
t
PZH
Enable Time
3.3
4.5
11.0
15.5
4.5
17.0
ns
DIR to A
n
or B
n
5.0
3.0
8.5
11.0
3.0
11.5
t
PZL
Enable Time
3.3
4.5
11.0
15.5
4.5
17.0
ns
DIR to A
n
or B
n
5.0
3.0
8.5
11.0
3.0
11.5
t
PHZ
Disable Time
3.3
1.5
8.0
11.0
1.5
12.0
ns
DIR to A
n
or B
n
5.0
1.0
5.0
7.5
1.0
8.0
t
PLZ
Disable Time
3.3
1.5
8.0
11.0
1.5
12.0
ns
DIR to A
n
or B
n
5.0
1.0
5.0
7.5
1.0
8.0
t
OS
Output to Output Skew (Note 15)
3.3
1.0
1.5
1.5
ns
5.0
0.5
1.0
1.0
Symbol
Parameter
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Units
(Note 16)
Typ
Guaranteed Minimum
t
S
Setup Time, HIGH or LOW
3.3
3.0
3.0
ns
Bus to Clock
5.0
3.0
3.0
t
H
Hold Time, HIGH or LOW
3.3
1.5
1.5
ns
Bus to Clock
5.0
1.5
1.5
t
W
Clock Pulse Width
3.3
4.0
4.0
ns
HIGH or LOW
5.0
4.0
4.0
7
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7
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AC
Q646
74AC
T
Q
6
4
6
AC Electrical Characteristics for ACTQ
Note 17: Voltage Range 5.0 is 5.0V
0.5V
Note 18: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device.
The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by
design. Not tested.
AC Operating Requirements for ACTQ
Note 19: Voltage Range 5.0 is 5.0V
0.5V
Capacitance
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Symbol
Parameter
(V)
C
L
=
50 pF
C
L
=
50 pF
Units
(Note 17)
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay
5.0
2.5
8.5
10.5
2.5
11.0
ns
t
PHL
Clock to Bus
t
PLH
Propagation Delay
5.0
2.0
8.0
10.0
2.0
10.5
ns
t
PHL
Bus to Bus
t
PLH
Propagation Delay
t
PHL
SBA or SAB to A
n
or B
n
5.0
2.5
8.5
10.5
2.5
11.0
ns
(w/A
n
or B
n
HIGH or LOW)
t
PZH
Enable Time
5.0
2.5
10.0
12.0
2.5
12.5
ns
t
PZL
G to A
n
or B
n
t
PHZ
Disable Time
5.0
1.0
7.0
8.5
1.0
9.0
ns
t
PLZ
G to A
n
or B
n
t
PZH
Enable Time
5.0
2.5
10.0
12.0
2.5
12.5
ns
t
PZL
DIR to A
n
or B
n
t
PHZ
Disable Time
5.0
1.0
7.0
8.5
1.0
9.0
ns
t
PLZ
DIR to A
n
or B
n
t
OSHL
Output to Output
t
OSLH
Skew (Note 18) Select to Bus
5.0
0.5
1.0
1.0
ns
or Clock to Bus
t
OSHL
Output to Output
t
OSLH
Skew (Note 18)
5.0
1.0
1.5
1.5
ns
Bus to Bus
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Symbol
Parameter
(V)
C
L
=
50 pF
C
L
=
50 pF
Units
(Note 19)
Typ
Guaranteed Minimum
t
S
Setup Time, HIGH or LOW
5.0
3.0
3.0
ns
Bus to Clock
t
H
Hold Time, HIGH or LOW
5.0
1.5
1.5
ns
Bus to Clock
t
W
Clock Pulse Width
5.0
4.0
4.0
ns
HIGH or LOW
Symbol
Parameter
Typ
Units
Conditions
C
IN
Input Capacitance
4.5
pF
V
CC
=
OPEN
C
I/O
Input/Output Capacitance
15.0
pF
V
CC
=
5.0V
C
PD
Power Dissipation Capacitance
90.0
pF
V
CC
=
5.0V
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8
74
A
C
Q646
7
4
AC
T
Q
646
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500
.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are at the
correct voltage.
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measure-
ment.
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
FIGURE 5. Quiet Output Noise Voltage Waveforms
Note 20: V
OHV
and V
OLP
are measured with respect to ground reference.
Note 21: Input pulses have the following characteristics: f
=
1 MHz,
t
r
=
3 ns, t
f
=
3 ns, skew
<
150 ps.
V
OLP
/V
OLV
and V
OHP
/V
OHV
:
Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50
coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
Measure V
OLP
and V
OLV
on the quiet output during the
worst case transition for active and enable. Measure
V
OHP
and V
OHV
on the quiet output during the worst
case active and enable transition.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
V
ILD
and V
IHD
:
Monitor one of the switching outputs using a 50
coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
First increase the input LOW voltage level, V
IL
,until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V
IL
limits, or on output HIGH levels that
exceed V
IH
limits. The input LOW voltage level at which
oscillation occurs is defined as V
ILD
.
Next decrease the input HIGH voltage level, V
IH
, until
the output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V
IL
limits, or on output HIGH levels that
exceed V
IH
limits. The input HIGH voltage level at which
oscillation occurs is defined as V
IHD
.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
FIGURE 6. Simultaneous Switching Test Circuit
9
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7
4
AC
Q646
74AC
T
Q
6
4
6
Physical Dimensions
inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
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10
74ACQ646
74ACTQ646
Quiet
Ser
i
es
Octa
l T
r
ansce
iver
/Regi
ste
r
wi
th 3-
S
T
A
T
E O
u
t
puts
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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