2000 Fairchild Semiconductor Corporation
DS010636
www.fairchildsemi.com
January 1990
Revised September 2000
7
4
AC
Q657 74AC
T
Q
6
5
7
Qui
e
t Seri
es
Oct
a
l Bidi
re
cti
onal T
r
a
n
sceiv
e
r w
i
th 8-
B
i
t
Par
i
t
y
Gener
a
tor
/
Checke
r
a
nd
3
-
ST
A
T
E
Output
s
74ACQ657 74ACTQ657
Quiet Series
Octal Bidirectional Transceiver with
8-Bit Parity Generator/Checker and 3-STATE Outputs
General Description
The ACQ/ACTQ657 contains eight non-inverting buffers
with 3-STATE outputs and an 8-bit parity generator/
checker. Intended for bus oriented applications, the device
combines the 245 and the 280 functions in one package.
The ACQ/ACTQ utilizes Fairchild Quiet Series
technol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series fea-
tures GTO
output control and undershoot corrector in
addition to a split ground bus or superior performance.
Features
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin skew AC performance
s
Combines the 245 and the 280 functions in one package
s
300 mil 24-pin slim dual-in-line package
s
Outputs source/sink 24 mA
s
ACTQ has TTL-compatible inputs
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT
, Quiet Series
, FACT Quiet Series
, and GTO
are trademarks of Fairchild Semiconductor Corporation.
Order Number
Package Number
Package Description
74ACQ657SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74ACTQ657SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACTQ657SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names
Description
A
0
A
7
Data Inputs/3-STATE Outputs
B
0
B
7
Data Inputs/3-STATE Outputs
T/R
Transmit/Receive Input
OE
Enable Input
PARITY
Parity Input/3-STATE Output
ODD/EVEN
ODD/EVEN Parity Input
ERROR
Error 3-STATE Output
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Functional Description
The Transmit/Receive (T/R) input determines the direction
of the data flow through the bidirectional transceivers.
Transmit (active HIGH) enables data from the A-Port to the
B-Port; Receive (active LOW) enables data from the B-Port
to the A-Port.
The Output Enable (OE) input disables the parity and
ERROR outputs and both the A and B Ports by placing
them in a HIGH-Z condition when the Output Enable input
is HIGH.
When transmitting (T/R HIGH), the parity generator detects
whether an even or odd number of bits on the A-Port are
HIGH and compares these with the condition of the parity
select (ODD/EVEN). If the Parity Select is HIGH and an
even number of A inputs are HIGH, the Parity output is
HIGH.
In receiving mode (T/R LOW), the parity select and number
of HIGH inputs on port B are compared to the condition of
the Parity input. If an even number of bits on the B-Port are
HIGH, the parity select is HIGH, and the PARITY input is
HIGH, then ERROR will be HIGH to indicate no error. If an
odd number of bits on the B-Port are HIGH, the parity
select is HIGH, and the PARITY input is HIGH, the ERROR
will be LOW indicating an error.
Function Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
Function Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Number of
Inputs
Input/
Outputs
Inputs That
Output
Are High
OE
T/R
ODD/EVEN
Parity
ERROR
Outputs Mode
0, 2, 4, 6, 8
L
H
H
H
Z
Transmit
L
H
L
L
Z
Transmit
L
L
H
H
H
Receive
L
L
H
L
L
Receive
L
L
L
H
L
Receive
L
L
L
L
H
Receive
1, 3, 5, 7
L
H
H
L
Z
Transmit
L
H
L
H
Z
Transmit
L
L
H
H
L
Receive
L
L
H
L
H
Receive
L
L
L
H
H
Receive
L
L
L
L
L
Receive
Immaterial
H
X
X
Z
Z
Z
Inputs
Outputs
OE
T/R
L
L
Bus B Data to Bus A
L
H
Bus A Data to Bus B
H
X
High-Z State
3
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AC
Q657
74AC
T
Q
6
5
7
Functional Block Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT
circuits outside databook specifications.
DC Electrical Characteristics for ACQ
Supply Voltage (V
CC
)
-
0.5V to
+
7.0V
DC Input Diode Current (I
IK
)
V
I
=
-
0.5V
-
20 MA
V
I
=
V
CC
+
0.5V
+
20 mA
DC Input Voltage (V
I
)
-
0.5V to V
CC
+
0.5V
DC Output Diode Current (I
OK
)
V
O
=
-
0.5V
-
20 mA
V
O
=
V
CC
+
0.5V
+
20 mA
DC Output Voltage (V
O
)
-
0.5V to V
CC
+
0.5V
DC Output Source
or Sink Current (I
O
)
50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
50 mA
Storage Temperature (T
STG
)
-
65
C to
+
150
C
DC Latch-up Source
Sink Current
300 mA
Junction Temperature (T
J
)
PDIP
140
C
Supply Voltage (V
CC
)
ACQ
2.0V to 6.0V
ACTQ
4.5V to 5.5V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
-
40
C to
+
85
C
Minimum Input Edge Rate
V/
t
ACQ Devices
V
IN
from 30% to 70% of V
CC
V
CC
@3.0V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate
V/
t
ACTQ Devices
V
IN
from 0.8V to 2.0V
V
CC
@4.5V, 5.5V
125 mV/ns
Symbol
Parameter
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
(V)
Typ
Guaranteed Limits
V
IH
Minimum HIGH Level
3.0
1.5
2.1
2.1
V
OUT
=
0.1V
Input Voltage
4.5
2.25
3.15
3.15
V
or V
CC
-
0.1V
5.5
2.75
3.85
3.85
V
IL
Maximum LOW Level
3.0
1.5
0.9
0.9
V
V
OUT
=
0.1V
Input Voltage
4.5
2.25
1.35
1.35
or V
CC
-
0.1V
5.5
2.75
1.65
1.65
V
OH
Minimum HIGH Level
3.0
2.99
2.9
2.9
V
Voltage Output
4.5
4.49
4.4
4.4
I
OUT
=
-
50
A
5.5
5.49
5.4
5.4
V
IN
=
V
IL
or V
IH
3.0
2.56
2.46
I
OH
=
-
12 mA
4.5
3.86
3.76
V
I
OH
=
-
24mA
5.5
4.85
4.76
I
OH
=
-
24 mA (Note 2)
V
OL
Maximum LOW Level
3.0
0.002
0.1
0.1
Output Voltage
4.5
0.001
0.1
0.1
V
I
OUT
=
50
A
5.5
0.001
0.1
0.1
V
V
IN
=
V
IL
or V
IH
3.0
0.36
0.44
I
OL
=
12 mA
4.5
0.36
0.44
I
OL
=
24 mA
5.5
0.36
0.44
I
OL
=
24 mA (Note 2)
I
IN
Maximum Input Leakage Current
5.5
0.1
1.0
A
V
I
=
V
CC
, GND
(Note 4)
(T/R, OE, ODD/EVEN Inputs)
I
OLD
Minimum Dynamic
5.5
75
mA
V
OLD
=
1.65V Max
I
OHD
Output Current (Note 3)
5.5
-
75
mA
V
OHD
=
3.85V Min
I
CC
(Note 4) Maximum Quiescent Supply Current
5.5
8.0
80.0
A
V
IN
=
V
CC
or GND
I
OZT
Maximum I/O Leakage Current
V
I
(OE)
=
V
IL
, V
IH
(A
n
, B
n
Inputs)
5.5
0.6
6.0
A
V
I
=
V
CC
, GND
V
O
=
V
CC
, GND
V
OLP
Quiet Output Maximum
5.0
1.1
1.5
V
Figures 1, 2
Dynamic V
OL
(Note 5)(Note 6)
5
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AC
Q657
74AC
T
Q
6
5
7
DC Electrical Characteristics for ACQ
(Continued)
Note 2: Maximum of 8 outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: I
IN
and I
CC
@ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V
CC
.
Note 5: DIP package.
Note 6: Max number of outputs defined as (n). Data Inputs are driven 0V to 5V. One output @ GND.
Note 7: Max number of Data Inputs (n) switching. (n
-
1) Inputs switching 0V to 5V (ACQ).Input-under-test switching: 5V to threshold (V
ILD
),
0V to threshold (V
IHD
) f
=
1 MHz.
DC Electrical Characteristics for ACTQ
Note 8: All outputs loaded; thresholds on input associated with output under test.
Note 9: Maximum test duration 2.0 ms, one output loaded at a time.
Note 10: DIP package.
Note 11: Max number of outputs defined as (n). n
-
1 Data Inputs are driven 0V to 3V; one output @ GND.
Note 12: Max number of Data Inputs (n) switching. (n
-
1) Inputs switching 0V to 3V (ACQ). Input-under-test switching; 3V to threshold (V
ILD
),
0V to threshold (V
IHD
) f
=
1 MHz.
Symbol
Parameter
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
(V)
Typ
Guaranteed Limits
V
OLV
Quiet Output Minimum
5.0
-
0.6
-
1.2
V
Figures 1, 2
Dynamic V
OL
(Note 5)(Note 6)
V
IHD
Minimum HIGH Level Dynamic
5.0
3.1
3.5
V
(Note 5)(Note 7)
Input Voltage
V
ILD
Maximum LOW Level Dynamic
5.0
1.9
1.5
V
(Note 5)(Note 7)
Input Voltage
Symbol
Parameter
V
CC
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
(V)
Typ
Guaranteed Limits
V
IH
Minimum HIGH Level
4.5
1.5
2.0
2.0
V
V
OUT
=
0.1V
Input Voltage
5.5
1.5
2.0
2.0
or V
CC
-
0.1V
V
IL
Maximum LOW Level
4.5
1.5
0.8
0.8
V
V
OUT
=
0.1V
Input Voltage
5.5
1.5
0.8
0.8
or V
CC
-
0.1V
V
OH
Minimum HIGH Level
4.5
4.49
4.4
4.4
V
I
OUT
=
-
50
A
Output Voltage
5.5
5.49
5.4
5.4
V
IN
=
V
IL
or V
IH
4.5
3.86
3.76
V
I
OH
=
-
24mA
5.5
4.86
4.76
I
OH
=
-
24 mA (Note 8)
V
OL
Maximum LOW Level
4.5
0.001
0.1
0.1
V
I
OUT
=
50
A
Output Voltage
5.5
0.001
0.1
0.1
V
IN
=
V
IL
or V
IH
4.5
0.36
0.44
V
I
OL
=
24 mA
5.5
0.36
0.44
I
OL
=
24 mA (Note 8)
I
IN
Maximum Input Leakage Current
5.5
0.1
1.0
A
V
I
=
V
CC
, GND
(T/R, OE, ODD/EVEN Inputs)
I
OZT
Maximum I/O Leakage Current
5.5
0.6
6.0
A
V
I
=
V
IL
, V
IH
(A
n
, B
n
Inputs)
5.5
V
O
=
V
CC
, GND
I
CCT
Maximum I
CC
/Input
5.5
0.6
1.5
mA
V
I
=
V
CC
-
2.1V
I
OLD
Minimum Dynamic
5.5
75
mA
V
OLD
=
1.65V Max
I
OHD
Output Current (Note 9)
5.5
-
75
mA
V
OHD
=
3.85V Min
I
CC
(Note 4) Maximum Quiescent Supply Current
5.5
8.0
80.0
A
V
IN
=
V
CC
or GND
V
OLP
Quiet Output Maximum
5.0
1.1
1.5
V
Figures 1, 2
Dynamic V
OL
(Note 10)(Note 11)
V
OLV
Quiet Output Minimum
5.0
-
0.6
-
1.2
V
Figures 1, 2
Dynamic V
OL
(Note 10)(Note 11)
V
IHD
Minimum HIGH Level Dynamic Input Voltage
5.0
1.9
2.2
V
(Note 10)(Note 12)
V
ILD
Maximum LOW Level Dynamic Input Voltage
5.0
1.2
0.8
V
(Note 10)(Note 12)
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AC Electrical Characteristics for ACQ
Note 13: Voltage Range 3.3 is 3.3V
0.3V
Voltage Range 5.0 is 5.0V
0.5V
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device.
The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by
design. Not tested.
Note 15: These delay times reflect the 3-STATE recovery time only and not the signal time through the buffers or the parity check circuitry. To assure VALID
information at the ERROR pin, time must be allowed for the signal to propagate through the drivers (B to A), through the parity check circuitry (same as A to
PARITY), and to the ERROR output after the ERROR pin has been enabled (Output Enable times). VALID data at the ERROR pin
(A to PARITY)
+
(Output
Enable Time).
V
CC
T
A
=
25
C
T
A
=
-
40
C to
+
85
C
Symbol
Parameter
(V)
C
L
=
50 pF
C
L
=
50 pF
Units
(Note 13)
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay
3.3
2.5
8.0
11.5
2.5
12.0
ns
t
PHL
A
n
to B
n
, B
n
to A
n
5.0
1.5
5.0
7.5
1.5
8.0
t
PLH
Propagation Delay
3.3
3.0
11.5
16.5
3.0
17.0
ns
t
PHL
A
n
to Parity
5.0
2.0
7.0
10.5
2.0
11.0
t
PLH
Propagation Delay
3.3
3.0
10.0
15.0
3.0
15.5
ns
t
PHL
ODD/EVEN to PARITY
5.0
2.5
6.5
10.0
2.5
10.5
t
PLH
Propagation Delay
3.3
3.0
10.0
15.0
3.0
15.5
ns
t
PHL
ODD/EVEN to ERROR
5.0
2.5
6.5
10.0
2.5
10.5
t
PLH
Propagation Delay
3.3
3.5
11.5
16.0
3.5
16.5
ns
t
PHL
B
n
to ERROR
5.0
2.5
7.0
10.5
2.5
11.0
t
PLH
Propagation Delay
3.3
3.0
9.0
13.5
3.0
14.0
ns
t
PHL
PARITY to ERROR
5.0
2.0
6.0
9.0
2.0
9.5
t
PZH
Output Enable Time
3.3
2.5
9.0
13.5
2.5
14.0
ns
t
PZL
OE to A
n
/B
n
5.0
2.0
6.0
9.0
2.0
9.5
t
PHZ
Output Disable Time
3.3
1.0
8.5
13.0
1.0
13.5
ns
t
PLZ
OE to A
n
/B
n
5.0
1.0
5.5
8.5
1.0
9.0
t
PZH
Output Enable Time
3.3
2.5
9.0
13.5
2.5
14.0
ns
t
PZL
OE to ERROR (Note 15)
5.0
2.0
6.0
9.0
2.0
9.5
t
PHZ
Output Disable Time
3.3
1.0
8.5
13.0
1.0
13.5
ns
t
PLZ
OE to ERROR
5.0
1.0
5.5
8.5
1.0
9.0
t
PZH
Output Enable Time
3.3
2.5
9.0
13.5
2.5
14.0
ns
t
PZL
OE to PARITY
5.0
2.0
6.0
9.0
2.0
9.5
t
PHZ
Output Disable Time
3.3
1.0
8.5
13.0
1.0
13.5
ns
t
PLZ
OE to PARITY
5.0
1.0
5.5
8.5
1.0
9.0
t
OSHL
Output to Output Skew (Note 14)
3.3
1.0
1.5
1.5
ns
t
OSLH
A
n
, B
n
to B
n
, A
n
5.0
0.5
1.0
1.0
7
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AC
Q657
74AC
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5
7
AC Electrical Characteristics for ACTQ
Note 16: Voltage Range 5.0 is 5.0V
0.5V
Note 17: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device.
The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by
design. Not tested.
Note 18: These delay times reflect the 3-STATE recovery time only and not the signal time through the buffers or the parity check circuitry. To assure VALID
information at the ERROR pin, time must be allowed for the signal to propagate through the drivers (B to A), through the parity check circuitry (same as A to
PARITY), and to the ERROR output after the ERROR pin has been enabled (Output Enable times). VALID data at the ERROR pin
(A to PARITY)
+
(Output
Enable Time).
Capacitance
V
CC
T
A
=
25
C
T
A
=
-
40
C to
+
85
C
Symbol
Parameter
(V)
C
L
=
50 pF
C
L
=
50 pF
Units
(Note 16)
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay
5.0
1.5
5.0
8.0
1.5
8.5
ns
t
PHL
A
n
to B
n
, B
n
to A
n
t
PLH
Propagation Delay
5.0
2.5
7.5
11.0
2.5
11.5
ns
t
PHL
A
n
to Parity
t
PLH
Propagation Delay
5.0
2.5
6.5
10.5
2.5
11.0
ns
t
PHL
ODD/EVEN to PARITY
t
PLH
Propagation Delay
5.0
2.5
6.5
10.5
2.5
11.0
ns
t
PHL
ODD/EVEN to ERROR
t
PLH
,
Propagation Delay
5.0
3.0
7.5
11.0
3.0
11.5
ns
t
PHL
B
n
to ERROR
t
PLH
Propagation Delay
5.0
2.0
6.0
9.5
2.0
10.0
ns
t
PHL
PARITY to ERROR
t
PZH
Output Enable Time
5.0
2.0
6.0
9.5
2.0
10.0
ns
t
PZL
OE to A
n
/B
n
t
PHZ
Output Disable Time
5.0
1.0
5.0
9.0
1.0
9.5
ns
t
PLZ
OE to A
n
/B
n
t
PZH
Output Enable Time
5.0
2.0
6.0
9.5
2.0
10.0
ns
t
PZL
OE to ERROR (Note 18)
t
PHZ
Output Disable Time
5.0
1.0
6.0
9.0
1.0
9.5
ns
t
PLZ
OE to ERROR
t
PZH
Output Enable Time
5.0
2.0
6.0
9.5
2.0
10.0
ns
t
PZL
OE to PARITY
t
PHZ
Output Disable Time
5.0
1.0
5.0
9.0
1.0
9.5
ns
t
PLZ
OE to PARITY
t
OSHL
Output to Output Skew
5.0
0.5
1.0
1.0
ns
t
OSLH
A
n
, B
n
to B
n
, A
n
(Note 17)
Symbol
Parameter
Typ
Units
Conditions
C
IN
Input Capacitance
4.5
pF
V
CC
=
5.0V
C
PD
Power Dissipation Capacitance
160.0
pF
V
CC
=
5.0
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8
74
A
C
Q657
7
4
AC
T
Q
657
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500
.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are at the
correct voltage.
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measure-
ment.
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
FIGURE 1. Quiet Output Noise Voltage Waveforms
Note 19: V
OHV
and V
OLP
are measured with respect to ground reference.
Note 20: Input pulses have the following characteristics: f
=
1 MHz,
t
r
=
3 ns, t
f
=
3 ns, skew
<
150 ps.
V
OLP
/V
OLV
and V
OHP
/V
OHV
:
Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50
coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
Measure V
OLP
and V
OLV
on the quiet output during the
worst case transition for active and enable. Measure
V
OHP
and V
OHV
on the quiet output during the worst
case transition.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
V
ILD
and V
IHD
:
Monitor one of the switching outputs using a 50
coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
First increase the input LOW voltage level, V
IL
, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V
IL
limits, or on output HIGH levels that
exceed V
IH
limits. The input LOW voltage level at which
oscillation occurs is defined as V
ILD
.
Next decrease the input HIGH voltage level, V
IH
, until
the output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V
IL
limits, or on output HIGH levels that
exceed V
IH
limits. The input HIGH voltage level at which
oscillation occurs is defined as V
IHD
.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
FIGURE 2. Simultaneous Switching Test Circuit
9
www.fairchildsemi.com
7
4
AC
Q657
74AC
T
Q
6
5
7
Physical Dimensions
inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
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10
74ACQ657
74
A
C
TQ657 Quie
t S
e
ri
es
Oct
a
l Bidi
rect
i
onal T
r
ans
ceive
r
wi
th 8-Bi
t Pari
ty
Genera
t
or
/Checker
an
d
3-
S
T
A
T
E O
u
t
puts
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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