2000 Fairchild Semiconductor Corporation
DS009170
www.fairchildsemi.com
October 1986
Revised February 2000
DM74ALS540A
Octal
I
nver
ti
ng Buf
f
er
and
Li
ne Dr
iver
wi
th
3-ST
A
T
E Out
puts
DM74ALS540A
Octal Inverting Buffer and Line Driver
with 3-STATE Outputs
General Description
This octal buffer and line driver is designed to have the per-
formance of the DM74ALS240A series and, at the same
time, offer a pinout with inputs and outputs on opposite
sides of the package. This arrangement greatly enhances
printed circuit board layout. The 3-STATE control gate is a
2-input NOR such that if either G1 or G2 is HIGH, all eight
outputs are in the high impedance state.
Features
s
Advanced oxide-isolated, ion-implanted Schottky TTL
process
s
Switching performance is guaranteed over full tempera-
ture and V
CC
supply range
s
Data flow-thru pinout (All inputs on opposite side from
outputs)
s
P-N-P inputs reduce DC loading
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Function Table
H
=
HIGH Logic Level
L
=
LOW Logic Level
X
=
Don't Care (Either HIGH or LOW Logic Level)
Hi-Z
=
High Impedance (OFF) State
Order Number
Package Number Package Description
DM74ALS540AWM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74ALS540ASJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74ALS540AN
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs
Output
G 1
G 2
A
Y
H
X
X
Hi-Z
X
H
X
Hi-Z
L
L
L
H
L
L
H
L
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2
DM
74ALS54
0A
Absolute Maximum Ratings
(Note 1)
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Recommended Operating Conditions
Electrical Characteristics
over recommended free air temperature range
Switching Characteristics
over recommended free air operating temperature range
Supply Voltage
7V
Input Voltage
7V
Voltage Applied to a
Disabled 3-STATE Output
5.5V
Operating Free-Air Temperature Range
0
C to
+
70
C
Storage Temperature Range
-
65
C to
+
150
C
Typical
JA
N Package
58.5
C/W
M Package
77.5
C/W
Symbol
Parameter
Min
Nom
Max
Units
V
CC
Supply Voltage
4.5
5
5.5
V
V
IH
HIGH Level Input Voltage
2
V
V
IL
LOW Level Input Voltage
0.7
V
I
OH
HIGH Level Output Current
-
15
mA
I
OL
LOW Level Output Current
24
mA
T
A
Free Air Operating Temperature
0
70
C
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
V
IK
Input Clamp Voltage
V
CC
=
Min, I
I
=
-
18 mA
-
1.5
V
V
OH
HIGH Level
V
CC
=
4.5V to 5.5V
I
OH
=
-
0.4 mA
V
CC
-
2
Output Voltage
V
CC
=
Min
I
OH
=
-
3 mA
2.4
3.2
V
I
OH
=
Max
2
V
OL
LOW
Level V
CC
=
Min
I
OL
=
12 mA
0.25
0.4
mA
Output Voltage
I
OL
=
24 mA
0.35
0.5
I
I
Input Current @ Maximum Input Voltage V
CC
=
Max, V
I
=
7V
100
A
I
IH
HIGH Level Input Current
V
CC
=
Max, V
I
=
2.7V
20
A
I
IL
LOW Level Input Current
V
CC
=
Max, V
I
=
0.4V
-
100
A
I
OZH
HIGH Level 3-STATE Output Current
V
CC
=
Max, V
O
=
2.7V
20
A
I
OZL
LOW Level 3-STATE Output Current
V
CC
=
Max, V
O
=
0.4V
-
20
A
I
O
Output Drive Current
V
CC
=
Max, V
O
=
2.25V
-
30
-
112
mA
I
CC
Supply Current
V
CC
=
Max
Outputs HIGH
5
10
Outputs LOW
13
22
mA
Outputs Disabled
11
19
Symbol
Parameter
Conditions
From (Input)
Min
Max
Units
To (Output)
t
PLH
Propagation Delay Time
V
CC
=
4.5V to 5.5V,
A or B to Y
2
12
ns
LOW-to-HIGH Level Output
R
1
=
R
2
=
500
,
t
PHL
Propagation Delay Time
C
L
=
50 pF
A or B to Y
2
9
ns
HIGH-to-LOW Level Output
t
PZH
Output Enable Time to HIGH Level Output
G to Y
5
15
ns
t
PZL
Output Enable Time to LOW Level Output
G to Y
8
20
ns
t
PHZ
Output Disable Time from HIGH Level Output
G to Y
1
10
ns
t
PLZ
Output Disable Time from LOW Level Output
G to Y
2
12
ns
3
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DM74ALS540A
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
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4
DM
74ALS54
0A
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
5
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DM74ALS540A
Octal
I
nver
ti
ng Buf
f
er
and
Li
ne Dr
iver
wi
th
3-ST
A
T
E Out
puts
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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