2002 Fairchild Semiconductor Corporation
DS500678
www.fairchildsemi.com
October 2001
Revised August 2002
7
4
AL
VC1624
5 Low
V
o
l
t
a
g
e 16-
Bit
Bi
di
rect
ional
T
r
anscei
ver
wit
h
3
.
6V
T
o
ler
a
nt
Inpu
ts
and Out
puts
74ALVC16245
Low Voltage 16-Bit Bidirectional Transceiver
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16245 contains sixteen non-inverting bidirec-
tional buffers with 3-STATE outputs and is intended for bus
oriented applications. The device is byte controlled. Each
byte has separate 3-STATE control inputs which can be
shorted together for full 16-bit operation. The T/R inputs
determine the direction of data flow through the device.
The OE inputs disable both the A and B ports by placing
them in a high impedance state.
The 74ALVC16245 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The 74ALVC16245 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s
1.65V3.6V V
CC
supply operation
s
3.6V tolerant inputs and outputs
s
t
PD
3.0 ns max for 3.0V to 3.6V V
CC
3.5 ns max for 2.3V to 2.7V V
CC
6.0 ns max for 1.65V to 1.95V V
CC
s
Power-down high impedance inputs and outputs
s
Supports live insertion/withdrawal (Note 1)
s
Uses patented noise/EMI reduction circuitry
s
Latchup conforms to JEDEC JED78
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
s
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Note 2: Ordering code "G" indicates Trays.
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Order Number
Package Number
Package Description
74ALVC16245G
(Note 2)(Note 3)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74ALVC16245MTD
(Note 3)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
www.fairchildsemi.com
2
74
A
L
VC16245
Connection Diagrams
Pin Assignment of TSSOP
Pin Assignment for FBGA
(Top Thru View)
Pin Descriptions
FBGA Pin Assignments
Truth Tables
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial (HIGH or LOW, inputs and I/O's may not float)
Z
=
High Impedance
Logic Diagram
Pin Names
Description
OE
n
Output Enable Input (Active LOW)
T/R
n
Transmit/Receive Input
A
0
A
15
Side A Inputs or 3-STATE Outputs
B
0
B
15
Side B Inputs or 3-STATE Outputs
NC
No Connect
1
2
3
4
5
6
A
B
0
NC
T/R
1
OE
1
NC
A
0
B
B
2
B
1
NC
NC
A
1
A
2
C
B
4
B
3
V
CC
V
CC
A
3
A
4
D
B
6
B
5
GND
GND
A
5
A
6
E
B
8
B
7
GND
GND
A
7
A
8
F
B
10
B
9
GND
GND
A
9
A
10
G
B
12
B
11
V
CC
V
CC
A
11
A
12
H
B
14
B
13
NC
NC
A
13
A
14
J
B
15
NC
T/R
2
OE
2
NC
A
15
Inputs
Outputs
OE
1
T/R
1
L
L
Bus B
0
B
7
Data to Bus A
0
A
7
L
H
Bus A
0
A
7
Data to Bus B
0
B
7
H
X
HIGH Z State on A
0
A
7
, B
0
B
7
Inputs
Outputs
OE
2
T/R
2
L
L
Bus B
8
B
15
Data to Bus A
8
A
15
L
H
Bus A
8
A
15
Data to Bus B
8
B
15
H
X
HIGH Z State on A
8
A
15
, B
8
B
15
3
www.fairchildsemi.com
7
4
AL
VC1624
5
Absolute Maximum Ratings
(Note 4)
Recommended Operating
Conditions
(Note 6)
Note 4: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The "Recommended Operating Conditions" table will define the condi-
tions for actual device operation.
Note 5: I
O
Absolute Maximum Rating must be observed.
Note 6: Floating or unused control inputs must be held HIGH or LOW.
DC Electrical Characteristics
Supply Voltage (V
CC
)
-
0.5V to
+
4.6V
DC Input Voltage (V
I
)
-
0.5V to 4.6V
Output Voltage (V
O
) (Note 5)
-
0.5V to V
CC
+
0.5V
DC Input Diode Current (I
IK
)
V
I
<
0V
-
50 mA
DC Output Diode Current (I
OK
)
V
O
<
0V
-
50 mA
DC Output Source/Sink Current
(I
OH
/I
OL
)
50 mA
DC V
CC
or GND Current per
Supply Pin (I
CC
or GND)
100 mA
Storage Temperature Range (T
STG
)
-
65
C to
+
150
C
Power Supply
Operating
1.65V to 3.6V
Input Voltage
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Free Air Operating Temperature (T
A
)
-
40
C to
+
85
C
Minimum Input Edge Rate (
t/
V)
V
IN
=
0.8V to 2.0V, V
CC
=
3.0V
10 ns/V
Symbol
Parameter
Conditions
V
CC
Min
Max
Units
(V)
V
IH
HIGH Level Input Voltage
1.65 - 1.95
0.65 x V
CC
V
2.3 - 2.7
1.7
2.7 - 3.6
2.0
V
IL
LOW Level Input Voltage
1.65 - 1.95
0.35 x V
CC
V
2.3 - 2.7
0.7
2.7 - 3.6
0.8
V
OH
HIGH Level Output Voltage
I
OH
=
-
100
A
1.65 - 3.6
V
CC
- 0.2
V
I
OH
=
-
4 mA
1.65
1.2
I
OH
=
-
6 mA
2.3
2.0
I
OH
=
-
12 mA
2.3
1.7
2.7
2.2
3.0
2.4
I
OH
=
-
24 mA
3.0
2
V
OL
LOW Level Output Voltage
I
OL
=
100
A
1.65 - 3.6
0.2
V
I
OL
=
4 mA
1.65
0.45
I
OL
=
6 mA
2.3
0.4
I
OL
=
12 mA
2.3
0.7
2.7
0.4
I
OL
=
24 mA
3.0
0.55
I
I
Input Leakage Current
0
V
I
3.6V
3.6
5.0
A
I
OZ
3-STATE Output Leakage
0
V
O
3.6V
3.6
10
A
I
CC
Quiescent Supply Current
V
I
=
V
CC
or GND, I
O
=
0
3.6
40
A
I
CC
Increase in I
CC
per Input
V
IH
=
V
CC
-
0.6V
3 - 3.6
750
A
5
www.fairchildsemi.com
7
4
AL
VC1624
5
AC Loading and Waveforms
FIGURE 1. AC Test Circuit
TABLE 1. Values for Figure 1
TABLE 2. Variable Matrix
(Input Characteristics: f
=
1MHz; t
r
=
t
f
=
2ns; Z
O
=
50
)
FIGURE 2. Waveform for Inverting and Non-inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
TEST
SWITCH
t
PLH
, t
PHL
Open
t
PZL
, t
PLZ
V
L
t
PZH
, t
PHZ
GND
Symbol
V
CC
3.3V
0.3V
2.7V
2.5
0.2V
1.8V
0.15V
V
mi
1.5V
1.5V
V
CC
/2
V
CC
/2
V
mo
1.5V
1.5V
V
CC
/2
V
CC
/2
V
X
V
OL
+
0.3V
V
OL
+
0.3V
V
OL
+
0.15V
V
OL
+
0.15V
V
Y
V
OH
-
0.3V
V
OH
-
0.3V
V
OH
-
0.15V
V
OH
-
0.15V
V
L
6V
6V
V
CC
*2
V
CC
*2
PDF 
ZIP