2002 Fairchild Semiconductor Corporation
DS500646
www.fairchildsemi.com
September 2001
Revised February 2002
7
4
AL
VC1628
35
Low V
o
l
t
a
ge
18
-Bit
U
n
iver
sal Bus D
r
ive
r
wi
th 3.
6V
T
o
l
e
rant
I
nputs
/
Outp
uts and
2
6
Seri
es
Res
i
st
ors in Output
s
74ALVC162835
Low Voltage 18-Bit Universal Bus Driver
with 3.6V Tolerant Inputs/Outputs
and 26
Series Resistors in Outputs
General Description
The ALVC162835 low voltage 18-bit universal bus driver
combines D-type latches and D-type flip-flops to allow data
flow in transparent, latched and clocked modes.
Data flow is controlled by output-enable (OE), latch-enable
(LE), and clock (CLK) inputs. The device operates in
Transparent Mode when LE is held HIGH. The device
operates in clocked mode when LE is LOW and CLK is tog-
gled. Data transfers from the Inputs (I
n
) to Outputs (O
n
) on
a Positive Edge Transition of the Clock. When OE is LOW,
the output data is enabled. When OE is HIGH the output
port is in a high impedance state.
The ALVC162835 is designed with 26
series resistors in
the outputs. This design reduces noise in applications such
as memory address drivers, clock drivers, and bus trans-
ceivers/transmitters.
The 74ALVC162835 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O capability up to 3.6V.
The 74ALVC162835 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s
Compatible with PC100 DIMM module specifications
s
1.65V to 3.6V V
CC
specifications provided
s
3.6V tolerant inputs and outputs
s
26
series resistors in outputs
s
t
PD
(CLK to O
n
)
5.4 ns max for 3.0V to 3.6V V
CC
6.3 ns max for 2.3V to 2.7V V
CC
9.2 ns max for 1.65V to 1.95V V
CC
s
Power-off high impedance inputs and outputs
s
Supports live insertion/withdrawal (Note 1)
s
Latchup conforms to JEDEC JED78
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Note 1: To ensure the high impedance state during power up or power
down, OE should be tied to V
CC
through a pulldown resistor; the minimum
value of the resistor is determined by the current sourcing capability of the
driver.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Order Number
Package
Number
Package Description
74ALVC162835T
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
www.fairchildsemi.com
2
74AL
VC162835
Connection Diagram
Pin Descriptions
Truth Table
H
=
Logic HIGH
L
=
Logic LOW
X
=
Don't Care, but not floating
Z
=
High Impedance
=
LOW-to-HIGH Clock Transition
Note 2: Output level before the indicated steady-state input conditions
were established provided that CLK was HIGH before LE went LOW.
Note 3: Output level before the indicated steady-state input conditions
were established.
Logic Diagram
Pin Names
Description
OE
Output Enable Input (Active LOW)
LE
Latch Enable Input
CLK
Clock Input
I
1
- I
18
Data Inputs
O
1
- O
18
3-STATE Outputs
Inputs
Outputs
OE
LE
CLK
I
n
O
n
H
X
X
X
Z
L
H
X
L
L
L
H
X
H
H
L
L
L
L
L
L
H
H
L
L
H
X
O
0
(Note 2)
L
L
L
X
O
0
(Note 3)
3
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7
4
AL
VC1628
35
Absolute Maximum Ratings
(Note 4)
Recommended Operating
Conditions
(Note 6)
Note 4: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The Recommended Operating Conditions tables will define the condi-
tions for actual device operation.
Note 5: I
O
Absolute Maximum Rating must be observed.
Note 6: Floating or unused pin (inputs or I/O's) must be held HIGH or LOW.
DC Electrical Characteristics
Supply Voltage (V
CC
)
-
0.5V to
+
4.6V
DC Input Voltage (V
I
)
-
0.5V to
+
4.6V
Output Voltage (V
O
) (Note 5)
-
0.5V to V
CC
+
0.5V
DC Input Diode Current (I
IK
)
V
I
<
0V
-
50 mA
DC Output Diode Current (I
OK
)
V
O
<
0V
-
50 mA
DC Output Source/Sink Current
(I
OH
/I
OL
)
50 mA
DC V
CC
or Ground Current per
Supply Pin (I
CC
or Ground)
100 mA
Storage Temperature Range (T
STG
)
-
65
C to
+
150
C
Power Supply
Operating
1.65V to 3.6V
Input Voltage
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Free Air Operating Temperature (T
A
)
-
40
C to
+
85
C
Minimum Input Edge Rate (
t/
V)
V
IN
=
0.8V to 2.0V, V
CC
=
3.0V
10 ns/V
Symbol
Parameter
Conditions
V
CC
Min
Max
Units
(V)
V
IH
HIGH Level Input Voltage
1.65 - 1.95
0.65 x V
CC
V
2.3 - 2.7
1.7
2.7 - 3.6
2.0
V
IL
LOW Level Input Voltage
1.65 - 1.95
0.35 x V
CC
V
2.3 - 2.7
0.7
2.7 - 3.6
0.8
V
OH
HIGH Level Output Voltage
I
OH
=
-
100
A
1.65 - 3.6
V
CC
- 0.2
V
I
OH
=
-
2 mA
1.65
1.2
I
OH
=
-
4 mA
2.3
1.9
I
OH
=
-
6 mA
2.3
1.7
3.0
2.4
I
OH
=
-
8 mA
2.7
2
I
OH
=
-
12 mA
3.0
2
V
OL
LOW Level Output Voltage
I
OL
=
100
A
1.65 - 3.6
0.2
V
I
OL
=
2 mA
1.65
0.45
I
OL
=
4 mA
2.3
0.4
I
OL
=
6 mA
2.3
0.55
3.0
0.55
I
OL
=
8 mA
2.7
0.6
I
OL
=
12 mA
3
0.8
I
I
Input Leakage Current
0
V
I
3.6V
3.6
5.0
A
I
OZ
3-STATE Output Leakage
0
V
O
3.6V
3.6
10
A
I
CC
Quiescent Supply Current
V
I
=
V
CC
or GND, I
O
=
0
3.6
40
A
I
CC
Increase in I
CC
per Input
V
IH
=
V
CC
-
0.6V
3 - 3.6
750
A
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4
74AL
VC162835
AC Electrical Characteristics
AC Electrical Characteristics Over Load
(Note 7)
Note 7: Characterized only.
Capacitance
Symbol
Parameter
T
A
=
-
40
C to
+
85
C, R
L
=
500
Units
C
L
=
50 pF
C
L
=
30 pF
V
CC
=
3.3V
0.3V
V
CC
=
2.7V
V
CC
=
2.5V
0.2V V
CC
=
1.8V
0.15V
Min
Max
Min
Max
Min
Max
Min
Max
f
CLOCK
Clock Frequency
150
150
150
100
MHz
t
W
Pulse Width LE High
3.3
3.3
3.3
4.0
ns
CLK High or Low
3.3
3.3
3.3
4.0
t
S
Setup Time
Data Before CLK
1.7
2.1
2.2
2.5
ns
Data Before CLK
CLK High
1.5
1.6
1.9
CLK Low
1.0
1.1
1.3
t
H
Hold Time
Data After CLK
0.7
0.6
0.6
1.0
ns
Data After LE
CLK High
1.4
1.7
1.4
or Low
f
MAX
Maximum Clock Frequency
150
150
150
100
MHz
t
PHL
, t
PLH
Propagation I to O
1.0
4.2
5.0
1.0
5.0
1.5
9.8
ns
Delay
LE to O
1.3
5.1
5.8
1.3
5.9
1.5
9.8
CLK to O
1.4
5.4
6.1
1.4
6.3
2.0
9.2
t
PZL
, t
PZH
Output Enable Time
1.1
5.5
6.5
1.4
6.3
1.5
9.8
ns
t
PLZ
, t
PHZ
Output Disable Time
1.3
4.5
4.9
1.0
4.9
1.5
7.9
ns
Symbol
Parameter
R
L
=
500
, V
CC
=
3.3V
0.15V
Units
T
A
=
-
0
C to
+
85
C T
A
=
-
0
C to
+
65
C
C
L
=
0 pF
C
L
=
50 pF
Min
Max
Min
Max
t
PHL
, t
PLH
Propagation Delay Bus to Bus
0.9
2.0
1.0
4.0
ns
t
PHL
, t
PLH
Propagation Delay Clock to Bus
1.4
2.9
1.9
5.0
ns
Symbol
Parameter
Conditions
T
A
=
+
25
C
Units
V
CC
Typical
C
IN
Input Capacitance
Control
V
I
=
0V or V
CC
3.3
3.5
pF
Data
V
I
=
0V or V
CC
3.3
5
C
OUT
Output Capacitance
V
I
=
0V, or V
CC
3.3
7
pF
C
PD
Power Dissipation Capacitance Outputs Enabled f
=
10 MHz, C
L
=
0 pF
3.3
40
pF
2.5
35
Outputs Disabled f
=
10 MHz, C
L
=
0 pF
3.3
14
2.5
125
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