2001 Fairchild Semiconductor Corporation
DS500713
www.fairchildsemi.com
December 2001
Revised December 2001
7
4
AL
VC1683
9 Low
V
o
l
t
a
g
e 20-
Bit
Sel
ect
able
Regi
ster
/Buf
fer
wi
th
3.6V
T
o
le
rant
I
nputs
and
Output
s
74ALVC16839
Low Voltage 20-Bit Selectable Register/Buffer
with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC16839 contains twenty non-inverting selectable
buffered or registered paths. The device can be configured
to operate in a registered, or flow through buffer mode by
utilizing the register enable (REGE) and Clock (CLK) sig-
nals. The device operates in a 20-bit word wide mode. All
outputs can be placed into 3-STATE through use of the OE
pin. These devices are ideally suited for buffered or regis-
tered 168 pin and 200 pin SDRAM DIMM memory mod-
ules.
The 74ALVC16839 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O compatibility up to 3.6V.
The 74ALVC16839 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s
Compatible with PC100 and PC133 DIMM module
specifications
s
1.65V to 3.6V V
CC
supply operation
s
3.6V tolerant inputs and outputs
s
t
PD
(CLK to O
n
)
3.7 ns max for 3.0V to 3.6V V
CC
4.9 ns max for 2.3V to 2.7V V
CC
8.8 ns max for 1.65V to 1.95V V
CC
s
Power-off high impedance inputs and outputs
s
Supports live insertion and withdrawal (Note 1)
s
Uses patented noise/EMI reduction circuitry
s
Latchup conforms to JEDEC JED78
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
Pin Descriptions
Order Number
Package Number
Package Descriptions
74ALVC16839MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names
Description
OE
Output Enable Input (Active LOW)
I
0
I
19
Inputs
O
0
O
19
Outputs
CLK
Clock Input
REGE
Register Enable Input
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2
74
A
L
VC16839
Connection Diagram
Truth Table
H
=
Logic HIGH
L
=
Logic LOW
X
=
Don't Care, but not floating
Z
=
High Impedance
=
LOW-to-HIGH Clock Transition
Functional Description
The 74ALVC16839 consists of twenty selectable non-
inverting buffers or registers with word wide modes. Mode
functionality is selected through operation of the CLK and
REGE pin as shown by the truth table. When REGE is held
at a logic HIGH the device operates as a 20-bit register.
Data is transferred from I
n
to O
n
on the rising edge of the
CLK input. When the REGE pin is held at a logic LOW the
device operates in a flow through mode and data propa-
gates directly from the I
n
to the O
n
outputs. All outputs can
be 3-stated by holding the OE pin at a logic HIGH.
Logic Diagram
Inputs
Outputs
CLK
REGE
I
n
OE
O
n
H
H
L
H
H
L
L
L
X
L
H
L
H
X
L
L
L
L
X
X
X
H
Z
3
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7
4
AL
VC1683
9
Absolute Maximum Ratings
(Note 2)
Recommended Operating
Conditions
(Note 4)
Note 2: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The "Recommended Operating Conditions" table will define the condi-
tions for actual device operation.
Note 3: I
O
Absolute Maximum Rating must be observed.
Note 4: Floating or unused inputs must be held HIGH or LOW.
DC Electrical Characteristics
Supply Voltage (V
CC
)
-
0.5V to
+
4.6V
DC Input Voltage (V
I
)
-
0.5V to 4.6V
Output Voltage (V
O
) (Note 3)
-
0.5V to V
CC
+
0.5V
DC Input Diode Current (I
IK
)
V
I
<
0V
-
50 mA
DC Output Diode Current (I
OK
)
V
O
<
0V
-
50 mA
DC Output Source/Sink Current
(I
OH
/I
OL
)
50 mA
DC V
CC
or GND Current per
Supply Pin (I
CC
or GND)
100 mA
Storage Temperature Range (T
STG
)
-
65
C to
+
150
C
Power Supply
Operating
1.65V to 3.6V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Free Air Operating Temperature (T
A
)
-
40
C to
+
85
C
Minimum Input Edge Rate (
t/
V)
V
IN
=
0.8V to 2.0V, V
CC
=
3.0V
10 ns/V
Symbol
Parameter
Conditions
V
CC
Min
Max
Units
(V)
V
IH
HIGH Level Input Voltage
1.65 -1.95
0.65 x V
CC
V
2.3 - 2.7
1.7
2.7 - 3.6
2.0
V
IL
LOW Level Input Voltage
1.65 -1.95
0.35 x V
CC
V
2.3 - 2.7
0.7
2.7 - 3.6
0.8
V
OH
HIGH Level Output Voltage
I
OH
=
-
100
A
1.65 - 3.6
V
CC
- 0.2
V
I
OH
=
-
4 mA
1.65
1.2
I
OH
=
-
6 mA
2.3
2
I
OH
=
-
12 mA
2.3
1.7
2.7
2.2
3.0
2.4
I
OH
=
-
24 mA
3.0
2
V
OL
LOW Level Output Voltage
I
OL
=
100
A
1.65 - 3.6
0.2
V
I
OL
=
4 mA
1.65
0.45
I
OL
=
6 mA
2.3
0.4
I
OL
=
12mA
2.3
0.7
2.7
0.4
I
OL
=
24 mA
3
0.55
I
I
Input Leakage Current
0
V
I
3.6V
3.6
5.0
A
I
OZ
3-STATE Output Leakage
0
V
O
3.6V
3.6
10
A
I
CC
Quiescent Supply Current
V
I
=
V
CC
or GND, I
O
=
0
3.6
40
A
I
CC
Increase in I
CC
per Input
V
IH
=
V
CC
-
0.6V
3 -3.6
750
A
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4
74
A
L
VC16839
AC Electrical Characteristics
Capacitance
Symbol
Parameter
T
A
=
-
40
C to
+
85
C, R
L
=
500
Units
C
L
=
50 pF
C
L
=
30 pF
V
CC
=
3.3V
0.3V
V
CC
=
2.7V
V
CC
=
2.5V
0.2V
V
CC
=
1.8V
0.15V
Min
Max
Min
Max
Min
Max
Min
Max
f
MAX
Maximum Clock Frequency
250
200
200
100
ns
t
PHL
, t
PLH
Propagation Delay
1.3
3.0
1.5
4.0
1.0
3.5
1.5
7.0
ns
Bus to Bus (REGE
=
0)
t
PHL
, t
PLH
Propagation Delay
1.3
3.7
1.5
4.9
1.0
4.4
1.5
8.8
ns
CLK to Bus (REGE
=
1)
t
PHL
, t
PLH
Propagation Delay
1.3
4.5
1.5
5.5
1.0
5.0
1.5
8.8
ns
REGE to Bus
t
PZL
, t
PZH
Output Enable Time
1.3
4.3
1.5
5.4
1.0
4.9
1.5
9.8
ns
t
PLZ
, t
PHZ
Output Disable Time
1.3
4.2
1.5
4.7
1.0
4.2
1.5
7.6
ns
t
W
Pulse Width
1.5
1.5
1.5
4.0
ns
t
S
Setup Time
1.0
1.0
1.0
2.5
ns
t
H
Hold Time
0.7
0.7
0.7
1.0
ns
Symbol
Parameter
Conditions
T
A
=
+
25
C
Units
V
CC
Typical
C
IN
Input Capacitance
V
I
=
0V or V
CC
3.3
6
pF
C
OUT
Output Capacitance
V
I
=
0V or V
CC
3.3
7
pF
C
PD
Power Dissipation Capacitance Outputs Enabled f
=
10 MHz, C
L
=
50 pF
3.3
20
pF
2.5
20
5
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7
4
AL
VC1683
9
AC Loading and Waveforms
AC Test Circuit
TABLE 1. Values for Figure
TABLE 2. Variable Matrix
(Input Characteristics: f
=
1MHz; t
r
=
t
f
=
2ns; Z
0
=
50
)
FIGURE 1. Waveform for Inverting and
Non-Inverting Functions
FIGURE 2. 3-STATE Output High Enable and
Disable Times for Low Voltage Logic
FIGURE 3. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
FIGURE 4. Propagation Delay, Pulse Width and
t
rec
Waveforms
FIGURE 5. Setup Time, Hold Time and
Recovery Time for Low Voltage Logic
TEST
SWITCH
t
PLH
, t
PHL
Open
t
PZL
, t
PLZ
V
L
t
PZH
, t
PHZ
GND
Symbol
V
CC
3.3V
0.3V
2.7V
2.5V
0.2V
1.8V
0.15V
V
mi
1.5V
1.5V
V
CC
/2
V
CC
/2
V
mo
1.5V
1.5V
V
CC
/2
V
CC
/2
V
X
V
OL
+
0.3V
V
OL
+
0.3V
V
OL
+
0.15V
V
OL
+
0.15V
V
Y
V
OH
-
0.3V
V
OH
-
0.3V
V
OH
-
0.15V
V
OH
-
0.15V
V
L
6V
6V
V
CC
*2
V
CC
*2
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