1999 Fairchild Semiconductor Corporation
DS009580
www.fairchildsemi.com
March 1988
Revised August 1999
7
4F646
74F646
B
7
4F648 O
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3-
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A
T
E Output
s
74F646 74F646B 74F648
Octal Transceiver/Register with 3-STATE Outputs
General Description
These devices consist of bus transceiver circuits with 3-
STATE, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the input bus
or from the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes
to a high logic level. Control G and direction pins are pro-
vided to control the transceiver function. In the transceiver
mode, data present at the high impedance port may be
stored in either the A or the B register or in both. The select
controls can multiplex stored and real-time (transparent
mode) data. The direction control determines which bus
will receive data when the enable control G is Active LOW.
In the isolation mode (control G HIGH), A data may be
stored in the B register and/or B data may be stored in the
A register.
Features
s
Independent registers for A and B buses
s
Multiplexed real-time and stored data
s
74F648 has inverting data paths
s
74F646/74F646B have non-inverting data paths
s
74F646B is a faster version of the 74F646
s
3-STATE outputs
s
300 mil slim DIP
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Order Number
Package Number
Package Description
74F646SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F646MSA
MSA24
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
74F646SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
74F646BSC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F646BSPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
74F648SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F648SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
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2
74F646
74F646B
74F648
Logic Symbols
74F646/74F646B
IEEE/IEC
74F646/74F646B
74F648
IEEE/IEC
74F648
Connection Diagrams
74F646/74F646B
74F648
3
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7
4F646
74F646
B
7
4F648
Unit Loading/Fan Out
Function Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Irrelevant
=
LOW-to-HIGH Transition
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR Inputs. Data input functions are always enabled; i.e., data
at the bus pins will be stored on every LOW-to-HIGH transition of the clock inputs.
Pin Names
Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
A
0
A
7
Data Register A Inputs/
3.5/1.083
70
A/
-
650
A
3-STATE Outputs
600/106.6 (80)
-
12 mA/64 mA (48 mA)
B
0
B
7
Data Register B Inputs/
3.5/1.083
70
A/
-
650
A
3-STATE Outputs
600/106.6 (80)
-
12 mA/64 mA (48 mA)
CPAB, CPBA
Clock Pulse Inputs
1.0/1.0
20
A/
-
0.6 mA
SAB, SBA
Select Inputs
1.0/1.0
20
A/
-
0.6 mA
G
Output Enable Input
1.0/1.0
20
A/
-
0.6 mA
DIR
Direction Control Input
1.0/1.0
20
A/
-
0.6 mA
Inputs
Data I/O (Note 1)
Function
G
DIR
CPAB CPBA
SAB
SBA
A
0
A
7
B
0
B
7
H
X
H or L H or L
X
X
Isolation
H
X
X
X
X
Input
Input
Clock A
n
Data into A Register
H
X
X
X
X
Clock B
n
Data into B Register
L
H
X
X
L
X
A
n
to B
n
--Real Time (Transparent Mode)
L
H
X
L
X
Input
Output
Clock A
n
Data into A Register
L
H
H or L
X
H
X
A Register to B
n
(Stored Mode)
L
H
X
H
X
Clock A
n
Data into A Register and Output to B
n
L
L
X
X
X
L
B
n
to A
n
--Real Time (Transparent Mode)
L
L
X
X
L
Output
Input
Clock B
n
Data into B Register
L
L
X
H or L
X
H
B Register to A
n
(Stored Mode)
L
L
X
X
H
Clock B
n
Data into B Register and Output to A
n
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4
74F646
74F646B
74F648
Logic Diagrams
74F646/74F646B
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F648
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
5
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7
4F646
74F646
B
7
4F648
Absolute Maximum Ratings
(Note 2)
Recommended Operating
Conditions
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 3: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
55
C to
+
125
C
Junction Temperature under Bias
-
55
C to
+
150
C
V
CC
Pin Potential to Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 3)
-
0.5V to
+
7.0V
Input Current (Note 3)
-
30 mA to
+
5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
-
0.5V to V
CC
3-STATE Output
-
0.5V to
+
5.5V
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
ESD Last Passing Voltage (Min)
4000V
Free Air Ambient Temperature
0
C to
+
70
C
Supply Voltage
+
4.5V to
+
5.5V
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized as a HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
Min
I
IN
=
-
18 mA (Non I/O Pins)
V
OH
Output HIGH
10% V
CC
2.0
V
Min
I
OH
=
-
15 mA (A
n
, B
n
)
Voltage
V
OL
Output LOW
10% V
CC
0.55
V
Min
I
OL
=
64 mA (A
n
, B
n
)
Voltage
I
IH
Input HIGH
5.0
A
Max
V
IN
=
2.7V (Non I/O Pins)
Current
I
BVI
Input HIGH Current
7.0
A
Max
V
IN
=
7.0V (Non I/O Pins)
Breakdown Test
I
BVIT
Input HIGH Current
0.5
mA
Max
V
IN
=
5.5V (A
n
, B
n
)
Breakdown (I/O)
I
CEX
Output HIGH
50
A
Max
V
OUT
=
V
CC
Leakage Current
V
ID
Input Leakage
4.75
V
0.0
I
ID
=
1.9
A
Test
All Other Pins Grounded
I
OD
Output Leakage
3.75
A
0.0
V
IOD
=
150 mV
Circuit Current
All Other Pins Grounded
I
IL
Input LOW Current
-
0.6
mA
Max
V
IN
=
0.5V (Non I/O Pins)
I
IH
+
I
OZH
Output Leakage Current
70
A
Max
V
OUT
=
2.7V (A
n
, B
n
)
I
IL
+
I
OZL
Output Leakage Current
-
650
A
Max
V
OUT
=
0.5V (A
n
, B
n
)
I
OS
Output Short-Circuit Current
-
100
-
225
mA
Max
V
OUT
=
0V
I
ZZ
Bus Drainage Test
500
A
0.0V
V
OUT
=
5.25V
I
CCH
Power Supply Current
135
mA
Max
V
O
=
HIGH
I
CCL
Power Supply Current
150
mA
Max
V
O
=
LOW
I
CCZ
Power Supply Current
150
mA
Max
V
O
=
HIGH Z
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6
74F646
74F646B
74F648
AC Electrical Characteristics
74F646/74F648
AC Operating Requirements
74F646/74F648
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
55
C to
+
125
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
V
CC
=
+
5.0V
C
L
=
50 pF
C
L
=
50 pF
C
L
=
50 pF
Min
Max
Min
Max
Min
Max
f
MAX
Maximum Clock Frequency
90
75
90
MHz
t
PLH
Propagation Delay
2.0
7.0
2.0
8.5
2.0
8.0
ns
t
PHL
Clock to Bus
2.0
8.0
2.0
9.5
2.0
9.0
t
PLH
Propagation Delay
1.0
7.0
1.0
8.0
1.0
7.5
ns
t
PHL
Bus to Bus (74F646)
1.0
6.5
1.0
8.0
1.0
7.0
t
PLH
Propagation Delay
2.0
8.5
1.0
10.0
2.0
9.0
ns
t
PHL
Bus to Bus (74F648)
1.0
7.5
1.0
9.0
1.0
8.0
t
PLH
Propagation Delay
2.0
8.5
2.0
11.0
2.0
9.5
ns
t
PHL
SBA or SAB to A or B
2.0
8.0
2.0
10.0
2.0
9.0
t
PZH
Enable Time
2.0
8.5
2.0
10.0
2.0
9.0
ns
t
PZL
OE to A or B
2.0
12.0
2.0
13.5
2.0
12.5
t
PHZ
Disable Time
1.0
7.5
1.0
9.0
1.0
8.5
ns
t
PLZ
OE to A or B
2.0
9.0
2.0
11.0
2.0
9.5
t
PZH
Enable Time
2.0
14.0
2.0
16.0
2.0
15.0
ns
t
PZL
DIR to A or B
2.0
13.0
2.0
15.0
2.0
14.0
t
PHZ
Disable Time
1.0
9.0
1.0
10.0
1.0
9.5
ns
t
PLZ
DIR to A or B
2.0
11.0
2.0
12.0
2.0
11.5
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
55
C to
+
125
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
V
CC
=
+
5.0V
Min
Max
Min
Max
Min
Max
t
S
(H)
Setup Time, HIGH or LOW
5.0
5.0
5.0
ns
t
S
(L)
Bus to Clock
5.0
5.0
5.0
t
H
(H)
Hold Time, HIGH or LOW
2.0
2.5
2.0
ns
t
H
(L)
Bus to Clock
2.0
2.5
2.0
t
W
(H)
Clock Pulse Width
5.0
5.0
5.0
ns
t
W
(L)
HIGH or LOW
5.0
5.0
5.0
7
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7
4F646
74F646
B
7
4F648
AC Electrical Characteristics
74F646B
AC Operating Requirements
74F646B
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
55
C to
+
125
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
V
CC
=
+
5.0V
C
L
=
50 pF
C
L
=
50 pF
C
L
=
50 pF
Min
Max
Min
Max
Min
Max
f
MAX
Maximum Clock Frequency
165
150
MHz
t
PLH
Propagation Delay
2.5
7.0
2.5
8.0
ns
t
PHL
Clock to Bus
3.0
7.5
3.0
8.0
t
PLH
Propagation Delay
2.0
6.0
2.0
7.0
ns
t
PHL
Bus to Bus
2.0
6.0
2.0
7.0
t
PLH
Propagation Delay
2.5
7.5
2.5
8.5
ns
t
PHL
SBA or SAB to A or B
2.5
7.5
2.5
8.5
t
PZH
Enable Time
2.5
6.5
2.5
8.0
ns
t
PZL
OE to A or B
2.5
9.0
2.5
10.0
t
PHZ
Disable Time
1.5
6.5
1.5
7.5
ns
t
PLZ
OE to A or B
2.0
7.0
2.0
8.5
t
PZH
Enable Time
2.0
7.0
2.0
8.5
ns
t
PZL
DIR to A or B
3.0
9.5
3.0
10.0
t
PHZ
Disable Time
1.5
7.5
1.5
8.5
ns
t
PLZ
DIR to A or B
2.5
8.5
2.5
9.5
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
55
C to
+
125
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
V
CC
=
+
5.0V
Min
Max
Min
Max
Min
Max
t
S
(H)
Setup Time, HIGH or LOW
5.0
4.0
ns
t
S
(L)
Bus to Clock
5.0
4.0
t
H
(H)
Hold Time, HIGH or LOW
1.5
1.5
ns
t
H
(L)
Bus to Clock
1.5
1.5
t
W
(H)
Clock Pulse Width
5.0
5.0
ns
t
W
(L)
HIGH or LOW
5.0
5.0
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8
74F646
74F646B
74F648
Physical Dimensions
inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
Package Number MSA24
9
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7
4F646
74F646
B
7
4F648 O
c
t
a
l
T
r
anscei
ver/
R
egist
er wit
h
3-
ST
A
T
E Output
s
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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