1999 Fairchild Semiconductor Corporation
DS009585
www.fairchildsemi.com
April 1988
Revised August 1999
7
4F673A 1
6
-Bi
t
Seri
al-
I
n,
Ser
i
al
/
P
aral
lel
-
Out
Shi
f
t
Regi
st
er
74F673A
16-Bit Serial-In, Serial/Parallel-Out Shift Register
General Description
The 74F673A contains a 16-bit serial-in, serial-out shift
register and a 16-bit Parallel-Out storage register. A single
pin serves either as an input for serial entry or as a 3-
STATE serial output. In the Serial-Out mode, the data recir-
culates in the shift register. By means of a separate clock,
the contents of the shift register are transferred to the stor-
age register for parallel outputting. The contents of the stor-
age register can also be parallel loaded back into the shift
register. A HIGH signal on the Chip Select input prevents
both shifting and parallel transfer. The storage register may
be cleared via STMR.
Features
s
Serial-to-parallel converter
s
16-bit serial I/O shift register
s
16-bit parallel-out storage register
s
Recirculating serial shifting
s
Recirculating parallel transfer
s
Common serial data I/O pin
s
Slim 24 lead package
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number
Package Number
Package Description
74F673ASC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F673APC
N24A
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide
74F673ASPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
www.fairchildsemi.com
2
74F67
3A
Unit Loading/Fan Out
Functional Description
The 16-bit shift register operates in one of four modes, as
indicated in the Shift Register Operations Table. A HIGH
signal on the Chip Select (CS) input prevents clocking and
forces the Serial Input/Output (SI/O) 3-STATE buffer into
the high impedance state. During serial shift-out opera-
tions, the SI/O buffer is active (i.e., enabled) and the output
data is also recirculated back into the shift register. When
parallel loading the shift register from the storage register,
serial shifting is inhibited.
The storage register has an asynchronous master reset
(STMR) input that overrides all other inputs and forces the
Q
0
Q
15
outputs LOW. The storage register is in the Hold
mode when either CS or the Read/Write (R/W) input is
HIGH. With CS and R/W both LOW, the storage register is
parallel loaded from the shift register.
Shift Register Operations Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
HIGH-to-LOW Transition
Storage Register Operations Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Transition
Pin Names
Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
CS
Chip Select Input (Active LOW)
1.0/1.0
20
A/
-
0.6 mA
SHCP
Shift Clock Pulse Input (Active Falling Edge)
1.0/1.0
20
A/
-
0.6 mA
STMR
Store Master Reset Input (Active LOW)
1.0/1.0
20
A/
-
0.6 mA
STCP
Store Clock Pulse Input
1.0/1.0
20
A/
-
0.6 mA
R/W
Read/Write Input
1.0/1.0
20
A/
-
0.6 mA
SI/O
Serial Data Input or
3.5/1.0
70
A/
-
0.6 mA
3-STATE Serial Output
150/40
-
3 mA/24 mA
Q
0
Q
15
Parallel Data Outputs
50/33.3
-
1 mA/20 mA
Control Inputs
SI/O
Operating Mode
CS R/W SHCP STCP
Status
H
X
X
X
High Z
Hold
L
L
X
Data In
Serial Load
L
H
L
Data Out Serial Output
with Recirculation
L
H
H
Active
Parallel Load;
No Shifting
Control Inputs
Operating
STMR
CS
R/W
STCP
Mode
L
X
X
X
Reset; Outputs LOW
H
H
X
X
Hold
H
X
H
X
Hold
H
L
L
Parallel Load
3
www.fairchildsemi.com
7
4F673A
Block Diagram
www.fairchildsemi.com
4
74F67
3A
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
55
C to
+
125
C
Junction Temperature under Bias
-
55
C to
+
150
C
V
CC
Pin Potential to Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 2)
-
0.5V to
+
7.0V
Input Current (Note 2)
-
30 mA to
+
5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
-
0.5V to V
CC
3-STATE Output
-
0.5V to
+
5.5V
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
Free Air Ambient Temperature
0
C to
+
70
C
Supply Voltage
+
4.5V to
+
5.5V
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized as a HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
Min
I
IN
=
-
18 mA (Non I/O pins)
V
OH
Output HIGH
10% V
CC
2.5
V
Min
I
OH
=
-
1 mA (Q
n
, SI/O)
Voltage
10% V
CC
2.4
I
OH
=
-
3 mA (SI/O)
5% V
CC
2.7
I
OH
=
-
1 mA (Q
n
, SI/O)
5% V
CC
2.7
I
OH
=
-
3 mA (SI/O)
V
OL
Output LOW
10% V
CC
0.5
V
Min
I
OL
=
20 mA (Q
n
)
Voltage
10% V
CC
0.5
I
OL
=
24 mA (SI/O)
I
IH
Input HIGH Current
20
A
Max
V
IN
=
2.7V (Non I/O pins)
I
BVI
Input HIGH Current
100
A
Max
V
IN
=
7.0V (Non I/O pins)
Breakdown Test
I
BVIT
Input HIGH Current
1.0
mA
Max
V
IN
=
5.5V (SI/O)
Breakdown Test (I/O)
I
IL
Input LOW Current
-
0.6
mA
Max
V
IN
=
0.5V
I
IH
+
Output Leakage
70
A
Max
V
OUT
=
2.7V (SI/O)
I
OZH
Current
I
IL
+
Output Leakage
-
650
A
Max
V
OUT
=
0.5V (SI/O)
I
OZL
Current
I
OS
Output Short-Circuit Current
-
60
-
150
mA
Max
V
OUT
=
0V
I
CEX
Output HIGH Leakage Current
250
A
Max
V
OUT
=
V
CC
I
ZZ
Bus Drainage Test
500
A
0.0V
V
OUT
=
5.25V
I
CCH
Power Supply Current
114
172
mA
Max
V
O
=
HIGH
I
CCL
Power Supply Current
114
172
mA
Max
V
O
=
LOW
5
www.fairchildsemi.com
7
4F673A
AC Electrical Characteristics
AC Operating Requirements
Symbol
Parameter
T
A
=
+
25
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
f
MAX
Maximum Clock Frequency
100
130
85
MHz
t
PLH
Propagation Delay
3.0
8.0
10.5
2.5
12.0
ns
t
PHL
STCP to Q
n
3.0
10.5
13.5
2.5
15.0
t
PHL
Propagation Delay
6.0
16.5
20.5
5.5
22.5
ns
STMR to Q
n
t
PLH
Propagation Delay
4.0
6.5
8.5
3.5
9.5
ns
t
PHL
SHCP to SI/O
4.5
8.0
10.5
4.0
12.0
t
PZH
Output Enable Time
5.0
8.5
11.0
4.0
12.5
ns
t
PZL
CS to SI/O
5.5
9.0
11.5
4.5
13.0
t
PHZ
Output Disable Time
3.5
5.5
7.5
3.0
8.5
t
PLZ
CS to SI/O
3.0
4.5
6.5
2.5
7.5
t
PZH
Output Enable Time
4.5
7.5
9.5
4.0
10.5
ns
t
PZL
R/W to SI/O
4.5
8.0
10.0
4.0
11.5
t
PHZ
Output Disable Time
3.0
5.5
7.0
2.5
8.0
t
PLZ
R/W to SI/O
2.5
4.0
5.5
2.0
6.5
Symbol
Parameter
T
A
=
+
25
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
Min
Max
Min
Max
t
S
(H)
Setup Time, HIGH or LOW
3.5
4.0
ns
t
S
(L)
CS or R/W to STCP
6.0
7.0
t
H
(H)
Hold Time, HIGH or LOW
0
0
t
H
(L)
CS or R/W to STCP
0
0
t
S
(H)
Setup Time, HIGH or LOW
3.0
3.5
ns
t
S
(L)
SI/O to SHCP
3.0
3.5
t
H
(H)
Hold Time, HIGH or LOW
3.0
3.5
t
H
(L)
SI/O to SHCP
3.0
3.5
www.fairchildsemi.com
6
74F67
3A
Physical Dimensions
inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide
Package Number N24A
7
www.fairchildsemi.com
7
4F673A 1
6
-Bi
t
Seri
al-
I
n,
Ser
i
al
/
P
aral
lel
-
Out
Shi
f
t
Regi
st
er
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
PDF 
ZIP