1999 Fairchild Semiconductor Corporation
DS009587
www.fairchildsemi.com
April 1988
Revised August 1999
7
4F675A 1
6
-Bi
t
Seri
al-
I
n,
Ser
i
al
/
P
aral
lel
-
Out
Shi
f
t
Regi
st
er
74F675A
16-Bit Serial-In, Serial/Parallel-Out Shift Register
General Description
The 74F675A contains a 16-bit serial in/serial out shift reg-
ister and a 16-bit parallel out storage register. Separate
serial input and output pins are provided for expansion to
longer words. By means of a separate clock, the contents
of the shift register are transferred to the storage register.
The contents of the storage register can also be loaded
back into the shift register. A HIGH signal on the Chip
Select input prevents both shifting and parallel loading.
Features
s
Serial-to-parallel converter
s
16-Bit serial I/O shift register
s
16-Bit parallel out storage register
s
Recirculating parallel transfer
s
Expandable for longer words
s
Slim 24 lead package
s
74F675A version prevents false clocking through
CS or R/W inputs
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number
Package Number
Package Description
74F675ASC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F675APC
N24A
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide
74F675ASPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
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2
74F67
5A
Unit Loading/Fan Out
Functional Description
The 16-Bit shift register operates in one of four modes, as
determined by the signals applied to the Chip Select (CS),
Read/Write (R/W) and Store Clock Pulse (STCP) input.
State changes are indicated by the falling edge of the Shift
Clock Pulse (SHCP). In the Shift Right mode, data enters
D
0
from the Serial Input (SI) pin and exits from Q
15
via the
Serial Data Output (SO) pin. In the Parallel Load mode,
data from the storage register outputs enter the shift regis-
ter and serial shifting is inhibited.
The storage register is in the Hold mode when either CS or
R/W is HIGH. With CS and R/W both LOW, the storage
register is parallel loaded from the shift register on the ris-
ing edge of STCP.
To prevent false clocking of the shift register, SHCP should
be in the LOW state during a LOW-to-HIGH transition of
CS. To prevent false clocking of the storage register, STCP
should be LOW during a HIGH-to-LOW transition of CS if
R/W is LOW, and should also be LOW during a HIGH-to-
LOW transition of R/W if CS is LOW.
Shift Register Operations Table
Storage Register Operations Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
HIGH-to-LOW Transition
=
LOW-to-HIGH Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names
Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
SI
Serial Data Input
1.0/1.0
20
A/
-
0.6 mA
CS
Chip Select Input (Active LOW)
1.0/1.0
20
A/
-
0.6 mA
SHCP
Shift Clock Pulse Input (Active Falling Edge)
1.0/1.0
20
A/
-
0.6 mA
STCP
Store Clock Pulse Input (Active Rising Edge)
1.0/1.0
20
A/
-
0.6 mA
R/W
Read/Write Input
1.0/1.0
20
A/
-
0.6 mA
SO
Serial Data Output
50/33.3
-
1 mA/20 mA
Q
0
Q
15
Parallel Data Outputs
50/33.3
-
1 mA/20 mA
Control Inputs
Operating
CS
R/W
SHCP STCP
Mode
H
X
X
X
Hold
L
L
X
Shift Right
L
H
L
Shift Right
L
H
H
Parallel Load,
No Shifting
Inputs
Operating
CS
R/W
STCP
Mode
H
X
X
Hold
L
H
X
Hold
L
L
Parallel Load
3
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7
4F675A
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
55
C to
+
125
C
Junction Temperature under Bias
-
55
C to
+
150
C
V
CC
Pin Potential to Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 2)
-
0.5V to
+
7.0V
Input Current (Note 2)
-
30 mA to
+
5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
-
0.5V to V
CC
3-STATE Output
-
0.5V to
+
5.5V
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
Free Air Ambient Temperature
0
C to
+
70
C
Supply Voltage
+
4.5V to
+
5.5V
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized as a HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
Min
I
IN
=
-
18 mA
V
OH
Output HIGH
10% V
CC
2.5
V
Min
I
OH
=
-
1 mA
Voltage
5% V
CC
2.7
I
OH
=
-
1 mA
V
OL
Output LOW
10% V
CC
0.5
V
Min
I
OL
=
20 mA
Voltage
I
IH
Input HIGH
5.0
A
Max
V
IN
=
2.7V
Current
I
BVI
Input HIGH Current
7.0
A
Max
V
IN
=
7.0V
Breakdown Test
I
CEX
Output HIGH
50
A
Max
V
OUT
=
V
CC
Leakage Current
V
ID
Input Leakage
4.75
V
0.0
I
ID
=
1.9
A
Test
All Other Pins Grounded
I
OD
Output Leakage
3.75
A
0.0
V
IOD
=
150 mV
Circuit Current
All Other Pins Grounded
I
IL
Input LOW Current
-
0.6
mA
Max
V
IN
=
0.5V
I
OS
Output Short-Circuit Current
-
60
-
150
mA
Max
V
OUT
=
0V
I
CCH
Power Supply Current
106
160
mA
Max
V
O
=
HIGH
I
CCL
Power Supply Current
106
160
mA
Max
V
O
=
LOW
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4
74F67
5A
AC Electrical Characteristics
AC Operating Requirements
Symbol
Parameter
T
A
=
+
25
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
f
MAX
Maximum Clock Frequency
100
130
85
MHz
t
PLH
Propagation Delay
3.0
8.0
10.5
2.5
12.0
ns
t
PHL
STCP to Q
n
3.0
10.5
13.5
2.5
15.0
t
PLH
Propagation Delay
4.0
7.0
9.5
3.5
10.5
ns
t
PHL
SHCP to SO
4.5
8.0
10.5
4.0
12.0
Symbol
Parameter
T
A
=
+
25
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
Min
Max
Min
Max
t
S
(H)
Setup Time, HIGH or LOW
3.5
4.0
t
S
(L)
CS or R/W to STCP
5.5
6.5
ns
t
H
(H)
Hold Time, HIGH or LOW
0
0
t
H
(L)
CS or R/W to STCP
0
0
t
S
(H)
Setup Time, HIGH or LOW
3.0
3.5
t
S
(L)
SI to SHCP
3.0
3.5
ns
t
H
(H)
Hold Time, HIGH or LOW
3.0
3.5
t
H
(L)
SI to SHCP
3.0
3.5
t
S
(H)
Setup Time, HIGH or LOW
6.5
7.5
t
S
(L)
R/W to SHCP
9.0
10.0
ns
t
H
(H)
Hold Time, HIGH or LOW
0
0
t
H
(L)
R/W to SHCP
0
0
t
S
(H)
Setup Time, HIGH or LOW
7.0
8.0
t
S
(L)
STCP to SHCP
7.0
8.0
ns
t
H
(H)
Hold Time, HIGH or LOW
0
0
t
H
(L)
STCP to SHCP
0
0
t
S
(H)
Setup Time, HIGH or LOW
3.0
3.5
t
S
(L)
CS to SHCP
3.0
3.5
ns
t
H
(H)
Hold Time, HIGH or LOW
3.0
3.5
t
H
(L)
CS to SHCP
3.0
3.5
t
W
(H)
SHCP Pulse Width
5.0
6.0
t
W
(L)
HIGH or LOW
5.0
6.0
ns
t
W
(H)
STCP Pulse Width
6.0
7.0
t
W
(L)
HIGH or LOW
5.0
6.0
t
S
(L)
SHCP to STCP
8.0
9.0
ns
t
H
(H)
SHCP to STCP
0.0
0.0
ns
5
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7
4F675A
Physical Dimensions
inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide
Package Number N24A
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6
74F675
A
16-
Bit
Ser
i
al
-I
n, Seri
al
/Par
all
e
l-
Out Shif
t Regis
t
er
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Package Number N24C
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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