1999 Fairchild Semiconductor Corporation
DS010977
www.fairchildsemi.com
March 1992
Revised August 1999
7
4FR74
74FR1074 Dual D-T
ype
Fl
ip-
F
lop
74FR74 74FR1074
Dual D-Type Flip-Flop
General Description
The 74FR74 and 74FR1074 are dual D-type flip-flops with
true and complement (Q/Q) outputs. On the 74FR74, data
at the D inputs is transferred to the outputs on the rising
edge of the clock input (CP
n
). The 74FR1074 is the nega-
tive edge triggered version of this device. Both parts fea-
ture asynchronous clear (C
Dn
) and set (S
Dn
) inputs which
are low level enabled.
Features
s
74FR74 is pin-for-pin compatible with the 74F74
s
True 150 MHz f
MAX
capability on 74FR74
s
Outputs sink 24 mA and source 24 mA
s
Guaranteed pin-to-pin skew specifications
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagrams
74FR74
74FR1074
Order Number
Package Number
Package Description
74FR74SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74FR74PC
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74FR1074SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74FR1074PC
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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2
74FR74
74FR1074
Logic Symbols
74FR74
74FR1074
Pin Descriptions
Truth Tables
74FR74
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
Z
=
High Impedance
X
=
Immaterial
=
Rising Edge
Q
0
=
Previous Q(Q) before LOW-to-HIGH Clock Transition
74FR1074
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
Z
=
High Impedance
X
=
Immaterial
=
Falling Edge
Q
0
=
Previous Q(Q) before HIGH-to-LOW Clock Transition
Pin Names
Description
D
n
Data Inputs
CP
n
Clock Inputs
S
Dn
Asynchronous Set Inputs
C
Dn
Asynchronous Clear Inputs
Q
n
True Output
Q
n
Complementary Output
Inputs
Outputs
SD
CD
CP
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H
H
H
H
H
H
L
H
H
L
L
H
H
H
L
X
Q
0
Q
0
Inputs
Outputs
SD
CD
CP
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H
H
H
H
H
H
L
H
H
L
L
H
H
H
L
X
Q
0
Q
0
3
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7
4FR74
74FR1074
Logic Diagrams
74FR74
74FR1074
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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4
74FR74
74FR1074
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
55
C to
+
125
C
Junction Temperature under Bias
-
55
C to
+
150
C
V
CC
Pin Potential to Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 2)
-
0.5V to
+
7.0V
Input Current (Note 2)
-
30 mA to
+
5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
-
0.5V to V
CC
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
ESD Last Passing Voltage (Min)
2000V
Free Air Ambient Temperature
0
C to
+
70
C
Supply Voltage
+
4.5V to
+
5.5V
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
Min
I
IN
=
-
18 mA
V
OH
Output HIGH
2.5
V
Min
I
OH
=
-
1 mA
Voltage
2.4
V
Min
I
OH
=
-
3 mA
2.0
V
Min
I
OH
=
-
24 mA
V
OL
Output LOW Voltage
0.5
V
Min
I
OL
=
24 mA
I
IH
Input HIGH Current
5
A
Max
V
IN
=
2.7V
I
BVI
Input HIGH Current
7
A
Max
V
IN
=
7.0V
Breakdown Test
I
IL
Input LOW Current
-
150
A
Max
V
IN
=
0.5V (D
n
, CP
n
)
-
1.8
mA
Max
V
IN
=
0.5V (C
Dn
, S
Dn
)
V
ID
Input Leakage Test
4.75
V
0.0
I
ID
=
1.9
A,
All Other Pins Grounded
I
OD
Output Circuit
3.75
V
0.0
V
IOD
=
150 mV,
Leakage Test
All Other Pins Grounded
I
OS
Output Short-Circuit Current
-
100
-
275
mA
Max
V
OUT
=
0.0V
I
CEX
Output HIGH
50
A
Max
V
OUT
=
V
CC
Leakage Current
I
CC
Power Supply Current
24
mA
Max
5
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7
4FR74
74FR1074
AC Electrical Characteristics
74FR74
Note 3: Pin-to-Pin Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged
device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
) or in opposite directions
both HL and LH (t
OST
). t
OST
is guaranteed by design.
AC Operating Requirements
74FR74
Note 4: This specification is guaranteed by design.
Symbol
Parameter
T
A
=
+
25
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
f
MAX
Maximum Clock Frequency
150
190
150
MHz
t
PLH
Propagation Delay
2.5
3.5
5.0
2.5
5.0
ns
t
PHL
CP
n
to Q
n
or Q
n
2.5
4.5
6.0
2.5
6.0
t
PLH
Propagation Delay
1.5
3.5
5.5
1.5
5.5
ns
t
PHL
C
Dn
or S
Dn
to Q
n
or Q
n
2.0
5.5
7.0
2.0
7.0
t
OSHL
Pin to Pin Skew
1.0
ns
(Note 3)
for HL Transitions
t
OSLH
Pin to Pin Skew
1.0
ns
(Note 3)
for LH Transitions
t
OST
Pin to Pin Skew
3.0
ns
(Note 3)
for HL/LH Transitions
t
Q/Q
True/Complement
1.8
ns
(Note 3)
Output Skew
t
PS
Pin (Signal)
1.8
ns
(Note 3)
Transition Variation
Symbol
Parameter
T
A
=
+
25
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
C
L
=
50 pF
C
L
=
50 pF
Min
Max
Min
Max
t
S
(H)
Setup Time, HIGH or LOW
2.5
2.5
ns
t
S
(L)
D
n
to CP
n
2.5
2.5
t
H
(H)
Hold Time, HIGH or LOW
0
0
ns
t
H
(L)
D
n
to CP
n
0
0
t
W
(H)
CP
n
Pulse Width
3.3
3.3
ns
t
W
(L)
HIGH or LOW
3.3
3.3
(Note 4)
t
W
(L)
S
Dn
or C
Dn
Pulse Width
4.0
4.0
ns
t
REC
Recovery Time
2.0
2.0
ns
S
Dn
or C
Dn
to CP
n
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6
74FR74
74FR1074
AC Electrical Characteristics
74FR1074
Note 5: Pin-to-Pin Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged
device. The specifications apply to any outputs switching in the same direction either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
) or in opposite directions
both HL and LH (t
OST
). t
OST
is guaranteed by design.
AC Operating Requirements
74FR1074
Note 6: This specification is guaranteed by design.
Symbol
Parameter
T
A
=
+
25
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
f
MAX
Maximum Clock Frequency
120
160
120
MHz
t
PLH
Propagation Delay
2.5
4.0
5.5
2.5
5.5
ns
t
PHL
CP
n
to Q
n
or Q
n
3.0
5.0
6.5
3.0
6.5
t
PLH
Propagation Delay
1.5
3.5
5.5
1.5
5.5
ns
t
PHL
C
Dn
or S
Dn
to Q
n
or Q
n
2.0
5.5
7.0
2.0
7.0
t
OSHL
Pin to Pin Skew
1.5
ns
(Note 5)
for HL Transitions
t
OSLH
Pin to Pin Skew
1.5
ns
(Note 5)
for LH Transitions
t
OST
Pin to Pin Skew
3.5
ns
(Note 5)
for HL/LH Transitions
t
Q/Q
True/Complement
2.0
ns
(Note 5)
Output Skew
t
PS
Pin (Signal)
2.0
ns
(Note 5)
Transition Variation
T
A
=
+
25
C
T
A
=
0
C
=
+
70
C
Symbol
Parameter
V
CC
=
+
5.0V
V
CC
=
+
5.0V
Units
C
L
=
50 pF
C
L
=
50 pF
Min
Max
Min
Max
t
S
(H)
Setup Time, HIGH or LOW
2.0
2.0
ns
t
S
(L)
D
n
to CP
n
2.0
2.0
t
H
(H)
Hold Time, HIGH or LOW
0
0
ns
t
H
(L)
D
n
to CP
n
0
0
t
W
(H)
CP
n
Pulse Width
3.3
3.3
ns
t
W
(L)
HIGH or LOW
3.3
3.3
(Note 6)
t
W
(L)
S
Dn
or C
Dn
Pulse Width
4.0
4.0
ns
t
REC
Recovery Time
2.0
2.0
ns
S
Dn
or C
Dn
to CP
n
7
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7
4FR74
74FR1074
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
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8
7
4FR74
74FR1074 Dual
D-T
ype
Fl
ip-
F
lo
p
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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