2001 Fairchild Semiconductor Corporation
DS012424
www.fairchildsemi.com
June 1998
Revised February 2001
7
4
LCX1
12
Low V
o
lt
age
Dual
J-K Negati
ve E
d
ge-T
r
i
gger
e
d Fli
p
-Fl
op w
i
th 5V T
o
l
e
ra
nt Input
s
74LCX112
Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop
with 5V Tolerant Inputs
General Description
The LCX112 is a dual J-K flip-flop. Each flip-flop has inde-
pendent J, K, PRESET, CLEAR, and CLOCK inputs with Q,
Q outputs. These devices are edge sensitive and change
state on the negative going transition of the clock pulse.
Clear and preset are independent of the clock and accom-
plished by a low logic level on the corresponding input.
LCX devices are designed for low voltage (3.3V or 2.5)
operation with the added capability of interfacing to a 5V
signal environment.
The 74LCX112 is fabricated with advanced CMOS technol-
ogy to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
s
5V tolerant inputs
s
2.3V3.6V V
CC
specifications provided
s
7.5 ns t
PD
max (V
CC
=
3.3V), 10
A I
CC
max
s
Power down high impedance inputs and outputs
s
24 mA output drive (V
CC
=
3.0V)
s
Implements patented noise/EMI reduction circuitry
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human body model
>
2000V
Machine
model
>
2000V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Order Number
Package Number
Package Description
74LCX112M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74LCX112SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX112MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names
Description
J
1
, J
2
, K
1
, K
2
Data Inputs
CP
1
, CP
2
Clock Pulse Inputs (Active Falling Edge)
C
D1
, C
D2
Direct Clear Inputs (Active LOW)
S
D1
, S
D2
Direct Set Inputs (Active LOW)
Q
1
, Q
2
, Q
1
, Q
2
Outputs
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2
74LCX1
12
Truth Table
(Each half)
H(h)
=
HIGH Voltage Level
L(l)
=
LOW Voltage Level
X
=
Immaterial
=
HIGH-to-LOW Clock Transition
Q
O
(Q
O
)
=
Before HIGH-to-LOW Transition of Clock
Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition.
Logic Diagram
Inputs
Outputs
S
D
C
D
CP
J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H
H
H
H
h
h
Q
O
Q
O
H
H
l
h
L
H
H
H
h
l
H
L
H
H
l
l
Q
O
Q
O
H
H
H
X
X
Q
O
Q
O
3
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74
L
C
X
1
1
2
Absolute Maximum Ratings
(Note 1)
Recommended Operating Conditions
(Note 3)
Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recom-
mended Operating Conditions" table will define the conditions for actual device operation.
Note 2: I
O
Absolute Maximum rating must be observed.
Note 3: Unused Inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
Parameter
Value
Conditions
Units
V
CC
Supply Voltage
-
0.5 to
+
7.0
V
V
I
DC Input Voltage
-
0.5 to
+
7.0
V
V
O
DC Output Voltage
-
0.5 to V
CC
+
0.5
Output in HIGH or LOW State (Note 2)
V
I
IK
DC Input Diode Current
-
50
V
I
<
GND
mA
I
OK
DC Output Diode Current
-
50
V
O
<
GND
mA
+
50
V
O
>
V
CC
I
O
DC Output Source/Sink Current
50
mA
I
CC
DC Supple Current per Supply Pin
100
mA
I
GND
DC Ground Current per Ground Pin
100
mA
T
STG
Storage Temperature
-
65 to 150
C
Symbol
Parameter
Min
Max
Units
V
CC
Supply Voltage
Operating
2.0
3.6
V
Data Retention
1.5
3.6
V
I
Input Voltage
0
5.5
V
V
O
Output Voltage
HIGH or LOW State
0
V
CC
V
I
OH
/I
OL
Output Current
V
CC
=
3.0V
-
3.6V
24
mA
V
CC
=
2.7V
-
3.0V
12
V
CC
=
2.3V
-
2.7V
8
T
A
Free-Air Operating Temperature
-
40
85
C
t/
V
Input Edge Rate, V
IN
=
0.8V
-
2.0V, V
CC
=
3.0V
0
10
ns/V
Symbol
Parameter
Conditions
V
CC
T
A
=
40
C to
+
85
C
Units
(V)
Min
Max
V
IH
HIGH Level Input Voltage
2.3
-
2.7
1.7
V
2.7
-
3.6
2.0
V
IL
LOW Level Input Voltage
2.3
-
2.7
0.7
V
2.7
-
3.6
0.8
V
OH
HIGH Level Output Voltage
I
OH
=
-
100
A
2.3
-
3.6
V
CC
- 0.2
0.7
V
I
OH
= -8 mA
2.3
1.8
I
OH
=
-
12 mA
2.7
2.2
I
OH
=
-
18 mA
3.0
2.4
I
OH
=
-
24 mA
3.0
2.2
V
OL
LOW Level Output Voltage
I
OL
=
100
A
2.3
-
3.6
0.6
I
OL
= 8mA
2.3
0.2
I
OL
=
12 mA
2.7
0.4
V
I
OL
=
16 mA
3.0
0.4
I
OL
=
24 mA
3.0
0.55
I
I
Input Leakage Current
0
I
I
5.5V
2.3
-
3.6
5.0
A
I
OFF
Power-Off Leakage Current
V
I
or V
O
=
5.5V
0
10
A
I
CC
Quiescent Supply Current
V
I
=
V
CC
or GND
2.3
-
3.6
10
A
3.6V
V
I
5.5V
2.3
-
3.6
10
A
I
CC
Increase in I
CC
per Input
V
IH
=
V
CC
-
0.6V
2.3
-
3.6
500
A
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4
74LCX1
12
AC Electrical Characteristics
Note 4: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
), or LOW-to-HIGH (t
OSLH
).
Dynamic Switching Characteristics
Capacitance
Symbol
Parameters
T
A
=
40
C to 85
C, R
L
=
500
Units
V
CC
=
3.3V
0.3V
V
CC
=
2.7V
V
CC
=
2.5V
0.2V
C
L
=
50 pF
C
L
=
50 pF
C
L
=
30 pF
Min
Max
Min
Max
Min
Max
f
MAX
Maximum Clock Frequency
150
150
150
MHz
t
PHL
Propagation Delay
1.5
7.5
1.5
8.0
1.5
9.0
ns
t
PLH
CP
n
to Q
n
or Q
n
1.5
7.5
1.5
8.0
1.5
9.0
t
PHL
Propagation Delay
1.5
7.0
1.5
8.0
1.5
8.4
ns
t
PLH
C
Dn
or S
Dn
to Q
n
or Q
n
1.5
7.0
1.7
8.0
1.5
8.4
t
S
Setup Time
2.5
2.5
4.0
ns
t
H
Hold Time
1.5
1.5
2.0
ns
t
W
Pulse Width CP
3.3
3.3
4.0
ns
t
W
Pulse Width (C
D
, S
D
)
3.3
3.3
4.0
ns
t
REC
Recovery Time
2.0
2.5
4.5
ns
t
OSHL
Output to Output Skew
1.0
ns
t
OSLH
(Note 4)
1.0
Symbol
Parameter
Conditions
V
CC
T
A
=
25
C
Units
(V)
Typical
V
OLP
Quiet Output Dynamic Peak V
OL
C
L
=
50 pF, V
IH
=
3.3V, V
IL
=
0V
3.3
0.8
V
C
L
=
30 pF, V
IH
=
2.5V, V
IL
=
0V
2.5
0.6
V
OLV
Quiet Output Dynamic Valley V
OL
C
L
=
50 pF, V
IH
=
3.3V, V
IL
=
0V
3.3
-
0.8
V
C
L
=
30 pF, V
IH
=
2.5V, V
IL
=
0V
2.5
-
0.6
Symbol
Parameter
Conditions
Typical
Units
C
IN
Input Capacitance
V
CC
=
Open, V
I
=
0V or V
CC
7
pF
C
OUT
Output Capacitance
V
CC
=
3.3V, V
I
=
0V or V
CC
8
pF
C
PD
Power Dissipation Capacitance
V
CC
=
3.3V, V
I
=
0V or V
CC
, f
=
10 MHz
25
pF
5
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74
L
C
X
1
1
2
AC Loading and Waveforms
Generic for LCX Family
FIGURE 1. AC Test Circuit
(C
L
includes probe and jig capacitance)
Waveform for Inverting and Non-Inverting Functions
Propagation Delay, Pulse Width and t
rec
Waveforms
3-STATE Output High Enable and
Disable TImes for Logic
3-STATE Output Low Enable and
Disable Times for Logic
Setup Time, Hold TIme and Recovery TIme for Logic
t
rise
and t
fall
FIGURE 2. Waveforms
(Input Pulse Characteristics; f=1MHz, t
r
=t
f
=3ns)
Test
Switch
t
PLH
, t
PHL
Open
t
PZL
, t
PLZ
6V at V
CC
=
3.3
0.3V
V
CC
x 2 at V
CC
=
2.5
0.2V
t
PZH
,t
PHZ
GND
Symbol
V
CC
3.3V
0.3V
2.7V
2.5V
0.2V
V
mi
1.5V
1.5V
V
CC
/2
V
mo
1.5V
1.5V
V
CC
/2
V
x
V
OL
+
0.3V
V
OL
+
0.3V
V
OL
+
0.15V
V
y
V
OH
-
0.3V
V
OH
-
0.3V
V
OH
-
0.15V
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