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Электронный компонент: 74LCXR162245MEX

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2005 Fairchild Semiconductor Corporation
DS500052
www.fairchildsemi.com
August 1998
Revised June 2005
7
4LCXR
1
62245
Low

V
o
lt
age
16-
Bit
Bi
dir
ecti
onal
T
r
anscei
ver
wit
h
5V
T
o
ler
ant
I
nput
s/
O
u
t
put
s
and 2
6
:
Seri
es
Res
i
st
ors in the

Outp
ut
s
Print form created on June 10, 2005 12:56 pm
74LCXR162245
Low Voltage 16-Bit Bidirectional Transceiver
with 5V Tolerant Inputs/Outputs
and 26
:
Series Resistors in the Outputs
General Description
The LCXR162245 contains sixteen non-inverting bidirec-
tional buffers with 3-STATE outputs and is intended for bus
oriented applications. The device is designed for low volt-
age (2.5V or 3.3V) V
CC
applications with capability of inter-
facing to a 5V signal environment. The device is byte
controlled. Each byte has separate control inputs which
could be shorted together for full 16-bit operation. The T/R
inputs determine the direction of data flow through the
device. The OE inputs disable both the A and B ports by
placing them in a high impedance state.
In addition, all A and B outputs include equivalent 26
:
(nominal) series resistors to reduce overshoot and under-
shoot and are designed to sink/source up to 12 mA at
V
CC
3.0V.
The LCXR162245 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Features
s
5V tolerant inputs and outputs
s
2.3V3.6V V
CC
specifications provided
s
A and B side outputs have equivalent 26
:
series
resistors
s
5.3 ns t
PD
max (V
CC
3.3V), 20
P
A I
CC
max
s
Power down high impedance inputs and outputs
s
Supports live insertion/withdrawal (Note 1)
s
Flow through pinout
s
Implements patented noise/EMI reduction circuitry
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human body model
!
2000V
Machine model
!
200V
Note 1: To ensure the high-impedance state during power up or down OE
should be tied to V
CC
through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "x" to the ordering code.
Logic Symbol
Pin Descriptions
Order Number
Package Number
Package Description
74LCXR162245MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[RAIL]
74LCXR162245MEX
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TAPE and REEL]
74LCXR162245MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[RAIL]
74LCXR162245MTX
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Pin Names
Description
OE
n
Output Enable Input
T/R
n
Transmit/Receive Input
A
0
A
15
Side A Inputs or 3-STATE Outputs
B
0
B
15
Side B Inputs or 3-STATE Outputs
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2
74LCXR162245
Connection Diagram
Truth Tables
Note 2: A and B port inputs are still active
Logic Diagram
Inputs
Outputs
OE
1
T/R
1
L
L
Bus B
0
B
7
Data to Bus A
0
A
7
L
H
Bus A
0
A
7
Data to Bus B
0
B
7
H
X
HIGH Z State on A
0
A
7
, B
0
B
7
(Note 2)
Inputs
Outputs
OE
2
T/R
2
L
L
Bus B
8
B
15
Data to Bus A
8
A
15
L
H
Bus A
8
A
15
Data to Bus B
8
B
15
H
X
HIGH Z State on A
8
A
15
, B
8
B
15
(Note 2)
3
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7
4LCXR
1
62245
Absolute Maximum Ratings
(Note 3)
Recommended Operating Conditions
(Note 5)
Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated
at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recom-
mended Operating Conditions" table will define the conditions for actual device operation.
Note 4: I
O
Absolute Maximum Rating must be observed.
Note 5: Unused pins (Inputs or I/O's) must be held HIGH or LOW. They may not Float.
DC Electrical Characteristics
Symbol
Parameter
Value
Conditions
Units
V
CC
Supply Voltage
0.5 to
7.0
V
V
I
DC Input Voltage
0.5 to
7.0
V
V
O
DC Output Voltage
0.5 to
7.0
Output in 3-STATE
V
0.5 to V
CC
0.5
Output in HIGH or LOW State (Note 4)
I
IK
DC Input Diode Current
50
V
I
GND
mA
I
OK
DC Output Diode Current
50
V
O
GND
mA
50
V
O
!
V
CC
I
O
DC Output Source/Sink Current
r
50
mA
I
CC
DC Supply Current per Supply Pin
r
100
mA
I
GND
DC Ground Current per Ground Pin
r
100
mA
T
STG
Storage Temperature
65 to
150
q
C
Symbol
Parameter
Min
Max
Units
V
CC
Supply Voltage
Operating
2.0
3.6
V
Data Retention
1.5
3.6
V
I
Input Voltage
0
5.5
V
V
O
Output Voltage
HIGH or LOW State
0
V
CC
V
3-STATE
0
5.5
I
OH
/I
OL
Output Current
V
CC
3.0V
3.6V
r
12
mA
V
CC
2.7V
3.0V
r
8
V
CC
2.3V
2.7V
r
4
T
A
Free-Air Operating Temperature
40
85
q
C
'
t/
'
V
Input Edge Rate, V
IN
0.8V2.0V, V
CC
3.0V
0
10
ns/V
Symbol
Parameter
Conditions
V
CC
T
A
40
q
C to
85
q
C
Units
(V) Min
Max
V
IH
HIGH Level Input Voltage
2.3
2.7
1.7
V
2.7
3.6
2.0
V
IL
LOW Level Input Voltage
2.3
2.7
0.7
V
2.7
3.6
0.8
V
OH
HIGH Level Output Voltage
I
OH
100
P
A 2.3
3.6
V
CC
0.2
V
I
OH
4 mA
2.3
1.8
I
OH
4 mA
2.7
2.2
I
OH
6 mA
3.0
2.4
I
OH
8 mA
2.7
2.0
I
OH
12 mA
3.0
2.0
V
OL
LOW Level Output Voltage
I
OL
100
P
A 2.3
3.6
0.2
V
I
OL
4 mA
2.3
0.6
I
OL
4 mA
2.7
0.4
I
OL
6 mA
3.0
0.55
I
OL
8 mA
2.7
0.6
I
OL
12 mA
3.0
0.8
I
I
Input Leakage Current
0
d
V
I
d
5.5V
2.3
3.6
r
5.0
P
A
I
OZ
3-STATE I/O Leakage
0
d
V
O
d
5.5V
2.3
3.6
r
5.0
P
A
V
I
V
IH
or V
IL
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4
74LCXR162245
DC Electrical Characteristics
(Continued)
Note 6: Outputs disabled or 3-STATE only.
AC Electrical Characteristics
Note 7: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by design.
Dynamic Switching Characteristics
Capacitance
Symbol
Parameter
Conditions
V
CC
T
A
40
q
C to
85
q
C
Units
(V) Min
Max
I
OFF
Power-Off Leakage Current
V
I
or V
O
5.5V
0
10
P
A
I
CC
Quiescent Supply Current
V
I
V
CC
or GND
2.3
3.6
20
P
A
3.6V
d
V
I
, V
O
d
5.5V (Note 6)
2.3
3.6
r
20
'
I
CC
Increase in I
CC
per Input
V
IH
V
CC
0.6V
2.3
3.6
500
P
A
Symbol
Parameter
T
A
40
q
C to
85
q
C, R
L
500
:
Units
V
CC
3.3V
r
0.3V
V
CC
2.7V
V
CC
2.5V
r
0.2
C
L
50 pF
C
L
50 pF
C
L
30 pF
Min
Max
Min
Max
Min
Max
t
PHL
Propagation Delay
1.5
5.3
1.5
6.0
1.5
6.4
ns
t
PLH
A
n
to B
n
or B
n
to A
n
1.5
5.3
1.5
6.0
1.5
6.4
t
PZL
Output Enable Time
1.5
7.3
1.5
8.0
1.5
9.5
ns
t
PZH
1.5
7.3
1.5
8.0
1.5
9.5
t
PLZ
Output Disable Time
1.5
6.4
1.5
6.9
1.5
7.7
ns
t
PHZ
1.5
6.4
1.5
6.9
1.5
7.7
t
OSHL
Output to Output Skew (Note 7)
1.0
ns
t
OSLH
1.0
Symbol
Parameter
Conditions
V
CC
T
A
25
q
C
Units
(V)
Typical
V
OLP
Quiet Output Dynamic Peak V
OL
C
L
50 pF, V
IH
3.3V, V
IL
0V
3.3
0.35
V
C
L
30 pF, V
IH
2.5V, V
IL
0V
2.5
0.25
V
OLV
Quiet Output Dynamic Valley V
OL
C
L
50 pF, V
IH
3.3V, V
IL
0V
3.3
0.35
V
C
L
30 pF, V
IH
2.5V, V
IL
0V
2.5
0.25
Symbol
Parameter
Conditions
Typical
Units
C
IN
Input Capacitance
V
CC
Open, V
I
0V or V
CC
7
pF
C
I/O
Input/Output Capacitance
V
CC
3.3V, V
I
0V or V
CC
8
pF
C
PD
Power Dissipation Capacitance
V
CC
3.3V, V
I
0V or V
CC
, f
10 MHz
20
pF
5
www.fairchildsemi.com
7
4LCXR
1
62245
AC LOADING and WAVEFORMS
Generic for LCX Family
FIGURE 1. AC Test Circuit (C
L
includes probe and jig capacitance)
Waveform for Inverting and Non-Inverting Functions
Propagation Delay. Pulse Width and t
rec
Waveforms
3-STATE Output Low Enable and
Disable Times for Logic
3-STATE Output High Enable and
Disable Times for Logic
Setup Time, Hold Time and Recovery Time for Logic
t
rise
and t
fall
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, t
R
= t
F
= 3ns)
Test
Switch
t
PLH
, t
PHL
Open
t
PZL
, t
PLZ
6V at V
CC
3.3
r
0.3V
V
CC
x 2 at V
CC
2.5
r
0.2V
t
PZH
,t
PHZ
GND
Symbol
V
CC
3.3V
r
0.3V
2.7V
2.5V
r
0.2V
V
mi
1.5V
1.5V
V
CC
/2
V
mo
1.5V
1.5V
V
CC
/2
V
x
V
OL
0.3V
V
OL
0.3V
V
OL
0.15V
V
y
V
OH
0.3V
V
OH
0.3V
V
OH
0.15V