74LVQ240
Low Voltage Octal Buffer/Line Driver with 3-STATE
Outputs
General Description
The LVQ240 is an inverting octal buffer and line driver de-
signed to be employed as a memory address driver, clock
driver and bus oriented transmitter or receiver which pro-
vides improved PC board density.
Features
n
Ideal for low power/low noise 3.3V applications
n
Implements patented EMI reduction circuitry
n
Available in SOIC JEDEC, SOIC EIAJ, and QSOP
packages
n
Guaranteed simultaneous switching noise level and
dynamic threshold performance
n
Improved latch-up immunity
n
Guaranteed incident wave switching into 75
n
4 kV minimum ESD immunity
Ordering Code:
Order Number
Package Number
Package Description
74LVQ240SC
M20B
20-Lead (0.300" Wide) Molded Small Outline Package, SOIC, JEDEC
74LVQ240SJ
M20D
20-Lead Molded Shrink Small Outline Package, SOIC, EIAJ
74LVQ240QSC
MQA20
20-Lead (0.150" Wide) Molded Shrink Small Outline Package, SSOP, JEDEC
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
Description
OE
1
, OE
2
3-STATE Output Enable Inputs
I
0
I
7
Inputs
O
0
O
7
Outputs
Connection Diagram
Truth Tables
Inputs
Outputs
OE
1
I
n
(Pins 12, 14, 16, 18)
L
L
H
L
H
L
H
X
Z
Inputs
Outputs
OE
2
I
n
(Pins 3, 5, 7, 9)
L
L
H
L
H
L
H
X
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
IEEE/IEC
DS011611-1
Pin Assignment,
SOIC and QSOP
DS011611-2
May 1998
74L
VQ240
Low
V
oltage
Octal
Buffer/Line
Driver
with
3-ST
A
T
E
Outputs
1998 Fairchild Semiconductor Corporation
DS011611
www.fairchildsemi.com
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
-0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= -0.5V
-20 mA
V
I
= V
CC
+ 0.5V
+20 mA
DC Input Voltage (V
I
)
-0.5V to V
CC
+ 0.5V
DC Output Diode Current (I
OK
)
V
O
= -0.5V
-20 mA
V
O
= V
CC
+ 0.5V
+20 mA
DC Output Voltage (V
O
)
-0.5V to V
CC
+ 0.5V
DC Output Source
or Sink Current (I
O
)
50 mA
DC V
CC
or Ground Current
(I
CC
or I
GND
)
400 mA
Storage Temperature (T
STG
)
-65C to +150C
DC Latch-Up Source or
Sink Current
300 mA
Recommended Operating
Conditions
(Note 2)
Supply Voltage (V
CC
)
2.0V to 3.6V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
-40C to +85C
Minimum Input Edge Rate (
V/
t)
V
IN
0.8V to 2.0V
V
CC
@
3.0V
125 mV/ns
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be op-
erated at these limits. The parametric values defined in the Electrical Charac-
teristics tables are not guaranteed at the absolute maximum ratings. The
"Recommended Operating Conditions" table will define the conditions for ac-
tual device operation.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
Parameter
V
CC
(V)
T
A
= +25C
T
A
= -40C to +85C
Units
Conditions
Typ
Guaranteed Limits
V
IH
Minimum High Level
Input Voltage
3.0
1.5
2.0
2.0
V
V
OUT
= 0.1V
or V
CC
- 0.1V
V
IL
Maximum Low Level
Input Voltage
3.0
1.5
0.8
0.8
V
V
OUT
= 0.1V
or V
CC
- 0.1V
V
OH
Minimum High Level
Output Voltage
3.0
2.99
2.9
2.9
V
I
OUT
= -50 A
3.0
2.58
2.48
V
V
IN
= V
IL
or V
IH
(Note 3)
I
OH
= -12 mA
V
OL
Maximum Low Level
Output Voltage
3.0
0.002
0.1
0.1
V
I
OUT
= 50 A
3.0
0.36
0.44
V
V
IN
= V
IL
or V
IH
(Note 3)
I
OL
= 12 mA
I
IN
Maximum Input
Leakage Current
3.6
0.1
1.0
A
V
I
= V
CC
, GND
I
OLD
Minimum Dynamic
Output Current (Note 4)
3.6
36
mA
V
OLD
= 0.8V Max (Note 5)
I
OHD
3.6
-25
mA
V
OHD
= 2.0V Min (Note 5)
I
CC
Maximum Quiescent
Supply Current
3.6
4.0
40.0
A
V
IN
= V
CC
or GND
I
OZ
Maximum 3-STATE
Leakage Current
3.6
0.25
2.5
A
V
I
(OE) = V
IL
, V
IH
V
I
= V
CC
, GND
V
O
= V
CC
, GND
V
OLP
Quiet Output
Maximum Dynamic V
OL
3.3
0.4
0.8
V
(Notes 6, 7)
V
OLV
Quiet Output
Minimum Dynamic V
OL
3.3
-0.4
-0.8
V
(Notes 6, 7)
V
IHD
Maximum High Level
Dynamic Input Voltage
3.3
1.6
2.0
V
(Notes 6, 8)
V
ILD
Maximum Low Level
Dynamic Input Voltage
3.3
1.6
0.8
V
(Notes 6, 8)
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: Incident wave switching on transmission lines with impedances as low as 75
for commercial temperature range is guaranteed for 74LVQ.
Note 6: Worst case package.
Note 7: Max number of outputs defined as (n). Data Inputs are driven 0V to 3.3V. One output
@
GND.
Note 8: Max number of Data Inputs (n) switching. n-1 Inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (V
ILD
), 0V to threshold (V
IHD
),
f = 1 MHz.
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2
AC Electrical Characteristics
Symbol
Parameter
V
CC
(V)
T
A
= +25C
C
L
= 50 pF
T
A
= -40C to +85C
C
L
= 50 pF
Units
Min
Typ
Max
Min
Max
t
PHL
Propagation Delay
2.7
2.0
8.4
14.0
2.0
15.0
ns
t
PLH
Data to Output
3.3
0.3
2.0
7.0
10.0
2.0
10.5
t
PZL
Output Enable Time
2.7
2.5
9.6
16.9
2.5
18.0
ns
t
PZH
3.3
0.3
2.5
8.0
12.0
2.5
12.5
t
PHZ
Output Disable Time
2.7
1.0
10.2
19.0
1.0
20.0
ns
t
PLZ
3.3
0.3
1.0
8.5
13.5
1.0
14.0
t
OSHL
Output to Output Skew
2.7
1.0
1.5
1.5
ns
t
OSLH
Data to Output (Note 9)
3.3
0.3
1.0
1.5
1.5
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The speci-
fication applies to any outputs switching in the same direction, either HIGH to LOW (t
OSHL
) or LOW to HIGH (t
OSLH
). Parameter guaranteed by design.
Capacitance
Symbol
Parameter
Typ
Units
Conditions
C
IN
Input Capacitance
4.5
pF
V
CC
= Open
C
PD
(Note 10)
Power Dissipation Capacitance
70
pF
V
CC
= 3.3V
Note 10: C
PD
is measured at 10 MHz.
3
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Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead (0.300" Wide) Molded Small Outline Package, SOIC, JEDEC
Package Number M20B
20-Lead Molded Shrink Small Outline Package, SOIC, EIAJ
Package Number M20D
5
www.fairchildsemi.com
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