74LVQ374
Low Voltage Octal D-Type Flip-Flop with 3-STATE
Outputs
General Description
The LVQ374 is a high-speed, low-power octal D-type flip-flop
featuring separate D-type inputs for each flip-flop and
3-STATE outputs for bus-oriented applications. A buffered
Clock (CP) and Output Enable (OE) are common to all
flip-flops.
Features
n
Ideal for low power/low noise 3.3V applications
n
Implements patented EMI reduction circuitry
n
Available in SOIC JEDEC, SOIC EIAJ and QSOP
packages
n
Guaranteed simultaneous switching noise level and
dynamic threshold performance
n
Improved latch-up immunity
n
Guaranteed incident wave switching into 75
n
4 kV minimum ESD immunity
n
Buffered positive edge-triggered clock
n
3-STATE outputs drive bus lines or buffer memory
address registers
Ordering Code:
Order Number
Package Number
Package Description
74LVQ374SC
M20B
20-Lead (0.300" Wide) Molded Small Outline Package, SOIC JEDEC
74LVQ374SJ
M20D
20-Lead Molded Shrink Small Outline Package, SOIC EIAJ
74LVQ374QSC
MQA20
20-Lead (0.150" Wide) Molded Shrink Small Outline Package, SOIC JEDEC
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbols
Connection Diagram
DS011360-1
IEEE/IEC
DS011360-2
Pin Assignment for
SOIC and QSOP
DS011360-3
May 1998
74L
VQ374
Low
V
oltage
Octal
D-T
ype
Flip-Flop
with
3-ST
A
T
E
Outputs
1998 Fairchild Semiconductor Corporation
DS011360
www.fairchildsemi.com
Pin Descriptions
Pin Names
Description
D
0
D
7
Data Inputs
CP
Clock Pulse Input
OE
3-STATE Output Enable Input
O
0
O
7
3-STATE Outputs
Truth Table
Inputs
Outputs
D
n
CP
OE
O
n
H
N
L
H
L
N
L
L
X
X
H
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
N
= LOW-to-HIGH Transition
Functional Description
The LVQ374 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE true outputs. The buff-
ered clock and buffered Output Enable are common to all
flip-flops. The eight flip-flops will store the state of their indi-
vidual D-type inputs that meet the setup and hold time re-
quirements on the LOW-to-HIGH Clock (CP) transition. With
the Output Enable (OE) LOW, the contents of the eight
flip-flops are available at the outputs. When the OE is HIGH,
the outputs go to the high impedance state. Operation of the
OE input does not affect the state of the flip-flops.
Logic Diagram
DS011360-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
-0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= -0.5V
-20 mA
V
I
= V
CC
+ 0.5V
+20 mA
DC Input Voltage (V
I
)
-0.5V to V
CC
+ 0.5V
DC Output Diode Current (I
OK
)
V
O
= -0.5V
-20 mA
V
O
= V
CC
+ 0.5V
+20 mA
DC Output Voltage (V
O
)
-0.5V to V
CC
+ 0.5V
DC Output Source
or Sink Current (I
O
)
50 mA
DC V
CC
or Ground Current
(I
CC
or I
GND
)
400 mA
Storage Temperature (T
STG
)
-65C to +150C
DC Latch-Up Source or
Sink Current
300 mA
Recommended Operating
Conditions
(Note 2)
Supply Voltage (V
CC
)
2.0V to 3.6V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
-40C to +85C
Minimum Input Edge Rate (
V/
t)
V
IN
from 0.8V to 2.0V
V
CC
@
3.0V
125 mV/ns
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be op-
erated at these limits. The parametric values defined in the Electrical Charac-
teristics tables are not guaranteed at the absolute maximum ratings. The
"Recommended Operating Conditions" table will define the conditions for ac-
tual device operation.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
Parameter
V
CC
(V)
T
A
= +25C
T
A
= -40C to +85C
Units
Conditions
Typ
Guaranteed Limits
V
IH
Minimum High Level
3.0
1.5
2.0
2.0
V
V
OUT
= 0.1V
Input Voltage
or V
CC
- 0.1V
V
IL
Maximum Low Level
3.0
1.5
0.8
0.8
V
V
OUT
= 0.1V
Input Voltage
or V
CC
- 0.1V
V
OH
Minimum High Level
3.0
2.99
2.9
2.9
V
I
OUT
= -50 A
Output Voltage
3.0
2.58
2.48
V
V
IN
= V
IL
or V
IH
(Note 3)
I
OH
= -12 mA
V
OL
Maximum Low Level
3.0
0.002
0.1
0.1
V
I
OUT
= 50 A
Output Voltage
3.0
0.36
0.44
V
V
IN
= V
IL
or V
IH
(Note 3)
I
OL
= 12 mA
I
IN
Maximum Input
3.6
0.1
1.0
A
V
I
= V
CC
, GND
Leakage Current
I
OLD
Minimum Dynamic
3.6
36
mA
V
OLD
= 0.8V Max (Note 5)
I
OHD
Output Current (Note 4)
3.6
-25
mA
V
OHD
= 2.0V Min (Note 5)
I
CC
Maximum Quiescent
3.6
4.0
40.0
A
V
IN
= V
CC
or GND
Supply Current
I
OZ
Maximum 3-STATE
V
I
(OE) = V
IL
, V
IH
Leakage Current
3.6
0.25
2.5
A
V
I
= V
CC
, GND
V
O
= V
CC
, GND
V
OLP
Quiet Output
3.3
0.5
0.8
V
(Notes 6, 7)
Maximum Dynamic V
OL
V
OLV
Quiet Output
3.3
-0.3
-0.8
V
(Notes 6, 7)
Minimum Dynamic V
OL
V
IHD
Maximum High Level
3.3
1.7
2.0
V
(Notes 6, 8)
Dynamic Input Voltage
V
ILD
Maximum Low Level
3.3
1.6
0.8
V
(Notes 6, 8)
Dynamic Input Voltage
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: Incident wave switching on transmission lines with impedances as low as 75
for commercial temperature range is guaranteed for 74LVQ.
Note 6: Worst case package.
Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND.
Note 8: Max number of Data Inputs (n) switching. (n - 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (V
ILD
), 0V to threshold (V
IHD
),
f = 1 MHz.
3
www.fairchildsemi.com
AC Electrical Characteristics
Symbol
Parameter
V
CC
(V)
T
A
= +25C
C
L
= 50 pF
T
A
= -40C to +85C
C
L
= 50 pF
Units
Min
Typ
Max
Min
Max
f
max
Maximum Clock Frequency
2.7
55
50
MHz
3.3
0.3
75
70
t
PLH
Propagation Delay
2.7
3.0
11.4
18.3
3.0
19.0
ns
t
PHL
CP to O
n
3.3
0.3
3.0
9.5
13.0
3.0
13.5
t
PZL
Output Enable Time
2.7
3.0
11.4
18.3
3.0
19.0
ns
t
PZH
3.3
0.3
3.0
9.5
13.0
3.0
13.5
t
PHZ
Output Disable Time
2.7
1.0
11.4
20.4
1.0
21.0
ns
t
PLZ
3.3
0.3
1.0
9.5
14.5
1.0
15.0
t
OSHL
Output to Output Skew (Note 9)
2.7
1.0
1.5
1.5
ns
t
OSLH
CP to O
n
3.3
0.3
1.0
1.5
1.5
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The speci-
fication applies to any outputs switching in the same direction, either HIGH to LOW (t
OSHL
) or LOW to HIGH (t
OSLH
). Parameter guaranteed by design.
AC Operating Requirements
Symbol
Parameter
V
CC
(V)
T
A
= +25C
C
L
= 50 pF
T
A
= 40C- to +85C
C
L
= 50 pF
Units
Typ
Guaranteed Minimum
t
S
Setup Time, HIGH or LOW
2.7
0
4.0
4.5
ns
D
n
to CP
3.3
0.3
0
3.0
3.0
t
H
Hold Time, HIGH or LOW
2.7
0
1.5
1.5
ns
D
n
to CP
3.3
0.3
0
1.5
1.5
t
W
CP Pulse Width,
2.7
2.4
5.0
6.0
ns
HIGH or LOW
3.3
0.3
2.0
4.0
4.0
Capacitance
Symbol
Parameter
Typ
Units
Conditions
C
IN
Input Capacitance
4.5
pF
V
CC
= Open
C
PD
(Note 10)
Power Dissipation Capacitance
39
pF
V
CC
= 3.3V
Note 10: C
PD
is measured at 10 MHz.
www.fairchildsemi.com
4
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead (0.300" Wide) Molded Small Outline Package, SOIC JEDEC
Package Number M20B
20-Lead Molded Shrink Small Outline Package, SOIC EIAJ
Package Number M20D
5
www.fairchildsemi.com
PDF 
ZIP