74LVQ74
Low Voltage Dual D-Type Positive Edge-Triggered
Flip-Flop
General Description
The LVQ74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs. In-
formation at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at a
voltage level of the clock pulse and is not directly related to
the transition time of the positive-going pulse. After the Clock
Pulse input threshold voltage has been passed, the Data in-
put is locked out and information present will not be trans-
ferred to the outputs until the next rising edge of the Clock
Pulse input.
Asynchronous Inputs:
LOW input to S
D
(Set) sets Q to HIGH level
LOW input to C
D
(Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes both Q and Q
HIGH
Features
n
Ideal for low power/low noise 3.3V applications
n
Guaranteed simultaneous switching noise level and
dynamic threshold performance
n
Guaranteed pin-to-pin skew AC performance
n
Guaranteed incident wave switching into 75
Ordering Code:
Order Number
Package Number
Package Description
74LVQ74SC
M14A
14-Lead (0.150" Wide) Molded Small Outline Integrated Circuit, SOIC JEDEC
74LVQ74SJ
M14D
14-Lead Molded Small Outline Package, SOIC EIAJ
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
Connection Diagram
DS011347-1
DS011347-2
IEEE/IEC
DS011347-3
Pin Assignment
for SOIC JEDEC and EIAJ
DS011347-4
May 1998
74L
VQ74
Low
V
oltage
Dual
D-T
ype
Positive
Edge-T
riggered
Flip-Flop
1998 Fairchild Semiconductor Corporation
DS011347
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Pin Descriptions
Pin Names
Description
D
1
, D
2
Data Inputs
CP
1
, CP
2
Clock Pulse Inputs
C
D1
, C
D2
Direct Clear Inputs
S
D1
, S
D2
Direct Set Inputs
Q
1
, Q
1
, Q
2
, Q
2
Outputs
Truth Table
Inputs
Outputs
S
D
C
D
CP
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H
H
H
H
N
H
H
L
H
H
N
L
L
H
H
H
L
X
Q
0
Q
0
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
N
= LOW-to-HIGH Clock Transition
Q
0
(Q
0
) = Previous Q(Q) before LOW-to-HIGH Transition of Clock
Logic Diagram
DS011347-6
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
-0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= -0.5V
-20 mA
V
I
= V
CC
+ 0.5V
+20 mA
DC Input Voltage (V
I
)
-0.5V to V
CC
+ 0.5V
DC Output Diode Current (I
OK
)
V
O
= -0.5V
-20 mA
V
O
= V
CC
+ 0.5V
+20 mA
DC Output Voltage (V
O
)
-0.5V to to V
CC
+ 0.5V
DC Output Source
or Sink Current (I
O
)
50 mA
DC V
CC
or Ground Current
(I
CC
or I
GND
)
200 mA
Storage Temperature (T
STG
)
-65C to +150C
DC Latch-Up Source or
Sink Current
100 mA
Recommended Operating
Conditions
(Note 2)
Supply Voltage (V
CC
)
2.0V to 3.6V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
-40C to +85C
Minimum Input Edge Rate (
V/
t)
V
IN
from 0.8V to 2.0V
V
CC
@
3.0V
125 mV/ns
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be op-
erated at these limits. The parametric values defined in the Electrical Charac-
teritics tables are not guaranteed at the absolute maximum ratings. The "Rec-
ommended Operating Conditions" table will define the conditions for actual
device operation.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol
Parameter
V
CC
(V)
T
A
= +25C
T
A
= -40C to +85C
Units
Conditions
Typ
Guaranteed Limits
V
IH
Minimum High Level
3.0
1.5
2.0
2.0
V
V
OUT
= 0.1V
or V
CC
- 0.1V
V
IL
Maximum Low Level
Input Voltage
3.0
1.5
0.8
0.8
V
V
OUT
= 0.1V
or V
CC
- 0.1V
V
OH
Minimum High Level
Output Voltage
3.0
2.99
2.9
2.9
V
I
OUT
= -50 A
3.0
2.58
2.48
V
V
IN
= V
IL
or V
IH
(Note 3)
I
OH
= -12 mA
V
OL
Maximum Low Level
Output Voltage
3.0
0.002
0.1
0.1
V
I
OUT
= 50 A
3.0
0.36
0.44
V
V
IN
= V
IL
or V
IH
(Note 3)
I
OL
= 12 mA
I
IN
Maximum Input
Leakage Current
3.6
0.1
1.0
A
V
I
= V
CC
, GND
I
OLD
Minimum Dynamic (Note 4)
Output Current
3.6
36
mA
V
OLD
= 0.8V Max (Note 5)
I
OHD
3.6
-25
mA
V
OHD
= 2.0V Min (Note 5)
I
CC
Maximum Quiescent
Supply Current
3.6
2.0
20.0
A
V
IN
= V
CC
or GND
V
OLP
Quiet Output
Maximum Dynamic V
OL
3.3
0.2
0.8
V
(Notes 6, 7)
V
OLV
Quiet Output
Minimum Dynamic V
OL
3.3
-0.2
-0.8
V
(Notes 6, 7)
V
IHD
Maximum High Level
Dynamic Input Voltage
3.3
1.7
2.0
V
(Notes 6, 8)
V
ILD
Maximum Low Level
Dynamic Input Voltage
3.3
1.6
0.8
V
(Notes 6, 8)
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: Incident wave switching on transmission lines with impedances as low as 75
for commercial temperature range is guaranteed for 74LVQ.
Note 6: Worst case package.
Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND.
Note 8: Max number of Data Inputs (n) switching. (n - 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (V
ILD
), 0V to threshold
(V
IHD
), f = 1 MHz.
3
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AC Electrical Characteristics
Symbol
Parameter
V
CC
(V)
T
A
= +25C
C
L
= 50 pF
T
A
= -40C to +85C
C
L
= 50 pF
Units
Min
Typ
Max
Min
Max
f
max
Maximum Clock
2.7
50
100
40
MHz
Frequency
3.3
0.3
100
125
95
t
PLH
Propagation Delay
2.7
3.5
9.6
16.9
3.5
19.0
ns
C
Dn
or S
Dn
to Q
n
3.3
0.3
3.5
8.0
12.0
2.5
13.0
t
PHL
Propagation Delay
2.7
4.0
12.6
16.9
3.5
19.0
ns
C
Dn
or S
Dn
to Q
n
3.3
0.3
4.0
10.5
12.0
3.5
13.5
t
PLH
Propagation Delay
2.7
4.5
9.6
19.0
4.0
23.0
ns
CP
n
to Q
n
or Q
n
3.3
0.3
4.5
8.0
13.5
4.0
16.0
t
PHL
Propagation Delay
2.7
3.5
9.6
19.7
3.5
21.0
ns
CP
n
to Q
n
or Q
n
3.3
0.3
3.5
8.0
14.0
3.5
14.5
t
OSHL
Output to Output Skew (Note 9)
2.7
1.0
1.5
1.5
ns
t
OSLH
Data to Output
3.3
0.3
1.0
1.5
1.5
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The speci-
fication applies to any outputs switching in the same direction, either HIGH to LOW (t
OSHL
) or LOW to HIGH (t
OSLH
). Parameter guaranteed by design.
AC Operating Requirements
Symbol
Parameter
V
CC
(V)
T
A
= +25C
C
L
= 50 pF
T
A
= -40C to +85C
C
L
= 50 pF
Units
Typ
Guaranteed Minimum
t
S
Set-up Time, HIGH or LOW
2.7
1.8
5.0
6.5
ns
3.3
0.3
1.5
4.0
4.5
t
H
Hold Time, HIGH or LOW
2.7
-2.4
0.5
0.5
ns
D
n
to CP
n
3.3
0.3
-2.0
0.5
0.5
t
W
Pulse Width
2.7
3.6
7.0
10.0
ns
3.3
0.3
3.0
5.5
7.0
t
rec
Recovery Time
2.7
-3.0
0
0
ns
3.3
0.3
-2.5
0
0
Capacitance
Symbol
Parameter
Typ
Units
Conditions
C
IN
Input Capacitance
4.5
pF
V
CC
= Open
C
PD
(Note 10)
Power Dissipation Capacitance
25
pF
V
CC
= 3.3V
Note 10: C
PD
is measured at 10 MHz.
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4
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead (0.150" Wide) Molded Small Outline Integrated Circuit, JEDEC (SC)
Package Number M14A
5
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