74LVQ86
Low Voltage Quad 2-Input Exclusive-OR Gate
General Description
The LVQ86 contains four 2-input exclusive-OR gates.
Features
n
Ideal for low power/low noise 3.3V applications
n
Guaranteed simultaneous switching noise level and
dynamic threshold performance
n
Guaranteed pin-to-pin skew AC performance
n
Guaranteed incident wave switching into 75
Ordering Code:
Order Number
Package Number
Package Description
74LVQ86SC
M14A
14-Lead (0.150" Wide) Molded Small Outline Package, SOIC JEDEC
74LVQ86SJ
M14D
14-Lead Small Outline Package, SOIC EIAJ
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
Description
A
0
A
3
Inputs
B
0
B
3
Inputs
O
0
O
3
Outputs
IEEE/IEC
DS011348-1
Pin Assignment
SOIC JEDEC and EIAJ
DS011348-2
May 1998
74L
VQ86
Low
V
oltage
Quad
2-Input
Exclusive-OR
Gate
1998 Fairchild Semiconductor Corporation
DS011348
www.fairchildsemi.com
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
-0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= -0.5V
-20 mA
V
I
= V
CC
+ 0.5V
+20 mA
DC Input Voltage (V
I
)
-0.5V to V
CC
+ 0.5V
DC Output Diode Current (I
OK
)
V
O
= -0.5V
-20 mA
V
O
= V
CC
+ 0.5V
+20 mA
DC Output Voltage (V
O
)
-0.5V to V
CC
+ 0.5V
DC Output Source
or Sink Current (I
O
)
50 mA
DC V
CC
or Ground Current
(I
CC
or I
GND
)
200 mA
Storage Temperature (T
STG
)
-65C to +150C
DC Latch-Up Source or
Sink Current
100 mA
Recommended Operating
Conditions
(Note 2)
Supply Voltage (V
CC
)
LVQ
2.0V to 3.6V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
74LVQ
-40C to +85C
Minimum Input Edge Rate (
V/
t)
V
IN
from 0.8V to 2.0V
V
CC
@
3.0V
125 mV/ns
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be op-
erated at these limits. The parametric values defined in the Electrical Charac-
teristics tables are not guaranteed at the absolute maximum ratings. The
"Recommended Operating Conditions" table will define the conditions for ac-
tual device operation .
Note 2: Unused inputs must be held HIGH or LOW.. They may not float.
DC Electrical Characteristics
Symbol
Parameter
V
CC
(V)
Units
Conditions
T
A
= 25C
T
A
= -40C to +85C
Typ
Guaranteed Limits
V
IH
Minimum High Level
3.0
1.5
2.0
2.0
V
V
OUT
= 0.1V
Input Voltage
or V
CC
- 0.1V
V
IL
Maximum Low Level
3.0
1.5
0.8
0.8
V
V
OUT
= 0.1V
Input Voltage
or V
CC
- 0.1V
V
OH
Minimum High Level
Output Voltage
3.0
2.99
2.9
2.9
V
I
OUT
= -50 A
3.0
2.58
2.48
V
V
IN
= V
IL
or V
IH
(Note 3)
I
OH
= -12 mA
V
OL
Maximum Low Level
Output Voltage
3.0
0.002
0.1
0.1
V
I
OUT
= 50 A
3.0
0.36
0.44
V
IN
= V
IL
or V
IH
(Note 3)
I
OL
= 12 mA
I
IN
Maximum Input
3.6
0.1
1.0
A
V
I
= V
CC
, GND
Leakage Current
I
OLD
Minimum Dynamic (Note 4)
3.6
36
mA
V
OLD
= 0.8V Max (Note 5)
I
OHD
Output Current
3.6
-25
mA
V
OHD
= 2.0V Min (Note 5)
I
CC
Maximum Quiescent
3.6
2.0
20.0
A
V
IN
= V
CC
or GND
Supply Current
V
OLP
Quiet Output
3.3
0.5
0.8
V
(Notes 6, 7)
Maximum Dynamic V
OL
V
OLV
Quiet Output
3.3
-0.5
-0.8
V
(Notes 6, 7)
Minimum Dynamic V
OL
V
IHD
Maximum High Level
3.3
1.8
2.0
V
(Notes 6, 8)
Dynamic Input Voltage
V
ILD
Maximum Low Level
3.3
1.8
0.8
V
(Notes 6, 8)
Dynamic Input Voltage
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 20 ms, one output loaded at a time.
Note 5: Incident wave switching on transmission lines with impedances as low as 75
for commercial temperature range is guaranteed for 74LVQ.
Note 6: Worst case package.
Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND.
Note 8: Max number of Data Inputs (n) switching. (n - 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (V
ILD
), 0V to threshold (V
IHD
),
f = 1 MHz.
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2
AC Electrical Characteristics
Symbol
Parameter
V
CC
(V)
T
A
= +25C
C
L
= 50 pF
T
A
= -40C to +85C
C
L
= 50 pF
Units
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay
2.7
2.0
7.2
16.2
1.5
18.0
ns
3.3
0.3
2.0
6.0
11.5
1.5
12.5
t
PHL
Propagation Delay
2.7
2.0
7.8
16.2
1.5
18.0
ns
3.3
0.3
2.0
6.5
11.5
1.5
12.5
t
OSHL
,
Output to Output Skew
2.7
1.0
1.5
1.5
ns
t
OSLH
(Note 9)
3.3
0.3
1.0
1.5
1.5
Note 9: Skews defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The speci-
fication applies to any outputs switching in the same direction, either HIGH to LOW (t
OSHL
) or LOW to HIGH (t
OSLH
). Parameter guaranteed by design.
Capacitance
Symbol
Parameter
Typ
Units
Conditions
C
IN
Input Capacitance
4.5
pF
V
CC
= Open
C
PD
(Note 10)
Power Dissipation Capacitance
23
pF
V
CC
= 3.3V
Note 10: C
PD
is measured at 10 MHz.
3
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Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead (0.150" Wide) Molded Small Outline Package, SOIC JEDEC
Package Number M14A
5
www.fairchildsemi.com
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