2005 Fairchild Semiconductor Corporation
DS500152
www.fairchildsemi.com
January 1999
Revised June 2005
7
4
L
V
T1
6245
74L
VTH16245 Low
V
o
l
t
age 16-Bi
t T
r
ansc
eiver
wi
th 3-ST
A
T
E
Out
put
s
74LVT16245 74LVTH16245
Low Voltage 16-Bit Transceiver with 3-STATE Outputs
General Description
The LVT16245 and LVTH16245 contain sixteen non-invert-
ing bidirectional buffers with 3-STATE outputs and is
intended for bus oriented applications. The device is byte
controlled. Each byte has separate control inputs which
can be shorted together for full 16-bit operation. The T/R
inputs determine the direction of data flow through the
device. The OE inputs disable both the A and B ports by
placing them in a high impedance state.
The LVTH16245 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These non-inverting transceivers are designed for low-volt-
age (3.3V) V
CC
applications, but with the capability to pro-
vide a TTL interface to a 5V environment. The LVT16245
and LVTH16245 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining low power dissipation.
Features
s
Input and output interface capability to systems at
5V V
CC
s
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH16245),
also available without bushold feature (74LVT16245).
s
Live insertion/extraction permitted
s
Power Up/Down high impedance provides glitch-free
bus loading
s
Outputs source/sink
32 mA/
64 mA
s
Functionally compatible with the 74 series 16245
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human-body model
!
2000V
Machine model
!
200V
Charged-device
!
1000V
s
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Ordering Code:
Note 1: BGA package available in Tape and Reel only.
Note 2: Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
Order Number
Package
Number
Package Description
74LVT16245GX
(Note 1)
BGA54A
(Preliminary)
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[Tape and Reel]
74LVT16245MEA
(Note 2)
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVT16245MTD
(Note 2)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH16245GX
(Note 1)
BGA54A
(Preliminary)
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[Tape and Reel]
74LVTH16245MEA
(Note 2)
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVTH16245MTD
(Note 2)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
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2
74L
VT16245
74L
VTH16245
Connection Diagrams
Pin Assignment for SSOP and TSSOP
Pin Assignment for FBGA
(Top Thru View)
Pin Descriptions
FBGA Pin Assignments
Truth Tables
H
HIGH Voltage Level
L
LOW Voltage Level
X
Immaterial
Z
High Impedance
Pin Names
Description
OE
n
Output Enable Input (Active LOW)
T/R
n
Transmit/Receive Input
A
0
A
15
Side A Inputs/3-STATE Outputs
B
0
B
15
Side B Inputs/3-STATE Outputs
NC
No Connect
1
2
3
4
5
6
A
B
0
NC
T/R
1
OE
1
NC
A
0
B
B
2
B
1
NC
NC
A
1
A
2
C
B
4
B
3
V
CC
V
CC
A
3
A
4
D
B
6
B
5
GND
GND
A
5
A
6
E
B
8
B
7
GND
GND
A
7
A
8
F
B
10
B
9
GND
GND
A
9
A
10
G
B
12
B
11
V
CC
V
CC
A
11
A
12
H
B
14
B
13
NC
NC
A
13
A
14
J
B
15
NC
T/R
2
OE
2
NC
A
15
Inputs
Outputs
OE
1
T/R
1
L
L
Bus B
0
B
7
Data to Bus A
0
A
7
L
H
Bus A
0
A
7
Data to Bus B
0
B
7
H
X
HIGHZ State on A
0
A
7
,B
0
B
7
Inputs
Outputs
OE
2
T/R
2
L
L
Bus B
8
B
15
Data to Bus A
8
A
15
L
H
Bus A
8
A
15
Data to Bus B
8
B
15
H
X
HIGHZ State on A
8
A
15
,B
8
B
15
3
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7
4
L
V
T1
6245
74L
VTH16245
Functional Description
The LVT16245 and LVTH16245 contain sixteen non-inverting bidirectional buffers with 3-STATE outputs. The device is byte
controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to
obtain full 16-bit operation.
Logic Diagrams
Note: Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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4
74L
VT16245
74L
VTH16245
Absolute Maximum Ratings
(Note 3)
Recommended Operating Conditions
Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 4: I
O
Absolute Maximum Ratings must be observed.
DC Electrical Characteristics
Symbol
Parameter
Value
Conditions
Units
V
CC
Supply Voltage
0.5 to
4.6
V
V
I
DC Input Voltage
0.5 to
7.0
V
V
O
Output Voltage
0.5 to
7.0
Output in 3-STATE
V
0.5 to
7.0
Output in HIGH or LOW State (Note 4)
I
IK
DC Input Diode Current
50
V
I
GND
mA
I
OK
DC Output Diode Current
50
V
O
GND
mA
I
O
DC Output Current
64
Output at HIGH State, V
O
!
V
CC
mA
128
Output at LOW State, V
O
!
V
CC
I
CC
DC Supply Current per Supply Pin
r
64
mA
I
GND
DC Ground Current per Ground Pin
r
128
mA
T
STG
Storage Temperature Range
65 to
150
q
C
Symbol
Parameter
Min
Max
Units
V
CC
Supply Voltage
2.7
3.6
V
V
I
Input Voltage
0
5.5
V
I
OH
HIGH-Level Output Current
32
mA
I
OL
LOW-Level Output Current
64
mA
T
A
Free-Air Operating Temperature
40
85
q
C
'
t/
'
V
Input Edge Rate, V
IN
0.8V2.0V, V
CC
3.0V
0
10
ns/V
Symbol
Parameter
V
CC
T
A
40
q
C to
85
q
C
Units
Conditions
(V)
Min
Max
V
IK
Input Clamp Diode Voltage
2.7
1.2
V
I
I
18 mA
V
IH
Input HIGH Voltage
2.73.6
2.0
V
V
O
d
0.1V or
V
IL
Input LOW Voltage
2.73.6
0.8
V
V
O
t
V
CC
0.1V
V
OH
Output HIGH Voltage
2.73.6
V
CC
0.2
V
I
OH
100
P
A
2.7
2.4
I
OH
8 mA
3.0
2.0
I
OH
32 mA
V
OL
Output LOW Voltage
2.7
0.2
V
I
OL
100
P
A
2.7
0.5
I
OL
24 mA
3.0
0.4
I
OL
16 mA
3.0
0.5
I
OL
32 mA
3.0
0.55
I
OL
64 mA
I
I(HOLD)
Bushold Input Minimum Drive
3.0
75
P
A
V
I
0.8V
(Note 5)
75
V
I
2.0V
I
I(OD)
Bushold Input Over-Drive
3.0
500
P
A
(Note 6)
(Note 5)
Current to Change State
500
(Note 7)
I
I
Input Current
3.6
10
P
A
V
I
5.5V
Control Pins
3.6
r
1
V
I
0V or V
CC
Data Pins
3.6
5
V
I
0V
1
V
I
V
CC
I
OFF
Power Off Leakage Current
0
r
100
P
A
0V
d
V
I
or V
O
d
5.5V
I
PU/PD
Power Up/Down 3-STATE
01.5
r
100
P
A
V
O
0.5V to 3.0V
Output Current
V
I
GND or V
CC
I
OZL
3-STATE Output Leakage Current
3.6
5
P
A
V
O
0.5V
I
OZL
3-STATE Output Leakage Current
3.6
5
P
A
V
O
0.0V
(Note 5)
5
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7
4
L
V
T1
6245
74L
VTH16245
DC Electrical Characteristics
(Continued)
Note 5: Applies to bushold versions only (74LVTH16245).
Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than V
CC
or GND.
Dynamic Switching Characteristics
(Note 9)
Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 10: Max number of outputs defined as (n). n
1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by design.
Capacitance
(Note 12)
Note 12: Capacitance is measured at frequency f
1 MHz, per MIL-STD-883, Method 3012.
Symbol
Parameter
V
CC
T
A
40
q
C to
85
q
C
Units
Conditions
(V)
Min
Max
I
OZH
3-STATE Output Leakage Current
3.6
5
P
A
V
O
3.0V
I
OZH
3-STATE Output Leakage Current
3.6
5
P
A
V
O
3.6V
(Note 5)
I
OZH
3-STATE Output Leakage Current
3.6
10
P
A
V
CC
V
O
d
5.5V
I
CCH
Power Supply Current
3.6
0.19
mA
Outputs HIGH
I
CCL
Power Supply Current
3.6
5.0
mA
Outputs LOW
I
CCZ
Power Supply Current
3.6
0.19
mA
Outputs Disabled
I
CCZ
Power Supply Current
3.6
0.19
mA
V
CC
d
V
O
d
5.5V,
Outputs Disabled
'
I
CC
Increase in Power Supply Current
3.6
0.2
mA
One Input at V
CC
0.6V
(Note 8)
Other Inputs at V
CC
or GND
Symbol
Parameter
V
CC
T
A
25
q
C
Units
Conditions
(V)
Min
Typ
Max
C
L
50 pF, R
L
500
:
V
OLP
Quiet Output Maximum Dynamic V
OL
3.3
0.8
V
(Note 10)
V
OLV
Quiet Output Minimum Dynamic V
OL
3.3
0.8
V
(Note 10)
Symbol
Parameter
T
A
40
q
C to
85
q
C
Units
C
L
50 pF, R
L
500
:
V
CC
3.3V
r
0.3V
V
CC
2.7V
Min
Max
Min
Max
t
PLH
Propagation Delay Data to Output
1.5
3.5
1.5
3.9
ns
t
PHL
1.3
3.5
1.3
3.9
t
PZH
Output Enable Time
1.5
4.5
1.5
5.3
ns
t
PZL
1.6
5.3
1.6
6.9
t
PHZ
Output Disable Time
2.3
5.4
2.3
6.1
ns
t
PLZ
2.2
5.1
2.2
5.4
t
OSHL
Output to Output Skew
1.0
1.0
ns
t
OSLH
(Note 11)
Symbol
Parameter
Conditions
Typical
Units
C
IN
Input Capacitance
V
CC
0V, V
I
0V or V
CC
4
pF
C
I/O
Input/Output Capacitance
V
CC
3.0V, V
O
0V or V
CC
8
pF
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