1999 Fairchild Semiconductor Corporation
DS012490
www.fairchildsemi.com
June 1999
Revised June 1999
7
4
L
V
T1
62240
74L
VTH162240
Low
V
o
l
t
ag
e 16-
Bit
I
nver
ti
ng Buf
f
er
/Li
ne
D
r
ive
r
w
i
th
3-
S
T
A
T
E
O
u
t
put
s and
25
Ser
i
es
Resi
stor
s i
n
the
Output
s
74LVT162240 74LVTH162240
Low Voltage 16-Bit Inverting Buffer/Line Driver
with 3-STATE Outputs and
25
Series Resistors in the Outputs
General Description
The LVT162240 and LVTH162240 contain sixteen inverting
buffers with 3-STATE outputs designed to be employed as
a memory and address driver, clock driver, or bus oriented
transmitter/receiver. The device is nibble controlled. Indi-
vidual 3-STATE control inputs can be shorted together for
8-bit or 16-bit operation.
The LVT162240 and LVTH162240 are designed with
equivalent 25
series resistance in both the HIGH and
LOW states of the output. This design reduces line noise in
applications such as memory address drivers, clock driv-
ers, and bus transceivers/transmitters.
The LVTH162240 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These inverting buffers and line drivers are designed for
low-voltage (3.3V) V
CC
applications, but with the capability
to provide a TTL interface to a 5V environment. The
LVT162240 and LVTH162240 are fabricated with an
advanced BiCMOS technology to achieve high speed oper-
ation similar to 5V ABT while maintaining a low power dis-
sipation.
Features
s
Input and output interface capability to systems at
5V V
CC
s
Outputs include equivalent series resistance of 25
to
make external termination resistors unnecessary and
reduce overshoot and undershoot
s
Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs (74LVTH162240),
also available without bushold feature (74LVT162240).
s
Live insertion/extraction permitted
s
Power Up/Down high impedance provides glitch-free
bus loading
s
Functionally compatible with the 74 series 162240
s
Latch-up performance exceeds 500 mA
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
Pin Descriptions
Order Number
Package Number
Package Description
74LVT162240MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVT162240MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH162240MEA
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVTH162240MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names
Description
OE
n
Output Enable Inputs (Active LOW)
I
0
I
15
Inputs
O
0
O
15
3-STATE Outputs
www.fairchildsemi.com
2
7
4
L
V
T1
62240
74L
VTH162240
Connection Diagram
Truth Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
Functional Description
The LVT162240 and LVTH162240 contain sixteen inverting
buffers with 3-STATE standard outputs. The device is nib-
ble (4 bits) controlled with each nibble functioning identi-
cally, but independent of the other. The control pins may be
shorted together to obtain full 16-bit operation. The 3-
STATE outputs are controlled by an Output Enable (OE
n
)
input for each nibble. When OE
n
is LOW, the outputs are in
2-state mode. When OE
n
is HIGH, the outputs are in the
high impedance mode, but this does not interfere with
entering new data into the inputs.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs
Outputs
OE
1
I
0
I
3
O
0
O
3
L
L
H
L
H
L
H
X
Z
Inputs
Outputs
OE
2
I
4
I
7
O
4
O
7
L
L
H
L
H
L
H
X
Z
Inputs
Outputs
OE
3
I
8
I
11
O
8
O
11
L
L
H
L
H
L
H
X
Z
Inputs
Outputs
OE
4
I
12
I
15
O
12
O
15
L
L
H
L
H
L
H
X
Z
3
www.fairchildsemi.com
7
4
L
V
T1
62240
74L
VTH162240
Absolute Maximum Ratings
(Note 1)
Recommended Operating Conditions
Note 1: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 2: I
O
Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol
Parameter
Value
Conditions
Units
V
CC
Supply Voltage
-
0.5 to
+
4.6
V
V
I
DC Input Voltage
-
0.5 to
+
7.0
V
V
O
Output Voltage
-
0.5 to
+
7.0
Output in 3-STATE
V
-
0.5 to
+
7.0
Output in HIGH or LOW State (Note 2)
I
IK
DC Input Diode Current
-
50
V
I
<
GND
mA
I
OK
DC Output Diode Current
-
50
V
O
<
GND
mA
I
O
DC Output Current
64
V
O
>
V
CC
Output at HIGH State
mA
128
V
O
>
V
CC
Output at LOW State
I
CC
DC Supply Current per Supply Pin
64
mA
I
GND
DC Ground Current per Ground Pin
128
mA
T
STG
Storage Temperature
-
65 to
+
150
C
Symbol
Parameter
Min
Max
Units
V
CC
Supply Voltage
2.7
3.6
V
V
I
Input Voltage
0
5.5
V
I
OH
HIGH-Level Output Current
-
12
mA
I
OL
LOW-Level Output Current
12
mA
T
A
Free Air Operating Temperature
-
40
+
85
C
t/
V
Input Edge Rate, V
IN
=
0.8V2.0V, V
CC
=
3.0V
0
10
ns/V
Symbol
Parameter
V
CC
(V)
T
A
=
-
40
C to
+
85
C
Units
Conditions
Min
Typ
Max
(Note 3)
V
IK
Input Clamp Diode Voltage
2.7
-
1.2
V
I
I
=
-
18 mA
V
IH
Input HIGH Voltage
2.73.6
2.0
V
V
O
0.1V or
V
O
V
CC
-
0.1V
V
IL
Input LOW Voltage
2.73.6
0.8
V
V
OH
Output HIGH Voltage
2.73.6
V
CC
-
0.2
V
I
OH
=
-
100
A
3.0
2.0
I
OH
=
-
12 mA
V
OL
Output LOW Voltage
2.7
0.2
V
I
OL
=
100
A
3.0
0.8
I
OL
=
12 mA
I
I(HOLD)
Bushold Input Minimum Drive
3.0
75
A
V
I
=
0.8V
(Note 4)
-
75
V
I
=
2.0V
I
I(OD)
Bushold Input Over-Drive
Current to Change State
3.0
500
A
(Note 5)
(Note 4)
-
500
(Note 6)
I
I
Input Current
3.6
10
A
V
I
=
5.5V
Control Pins
3.6
1
V
I
=
0V or V
CC
Data Pins
3.6
-
5
V
I
=
0V
1
V
I
=
V
CC
I
OFF
Power Off Leakage Current
0
100
A
0V
V
I
or V
O
5.5V
I
PU/PD
Power Up/Down
01.5V
100
A
V
O
=
0.5V to 3.0V
3-STATE Current
V
I
=
GND or V
CC
I
OZL
3-STATE Output Leakage Current
3.6
-
5
A
V
O
=
0.5V
I
OZH
3-STATE Output Leakage Current
3.6
5
A
V
O
=
3.0V
I
OZH
+
3-STATE Output Leakage Current
3.6
10
A
V
CC
<
V
O
5.5V
I
CCH
Power Supply Current
3.6
0.19
mA
Outputs HIGH
I
CCL
Power Supply Current
3.6
5
mA
Outputs LOW
I
CCZ
Power Supply Current
3.6
0.19
mA
Outputs Disabled
www.fairchildsemi.com
4
7
4
L
V
T1
62240
74L
VTH162240
DC Electrical Characteristics
(Continued)
Note 3: All typical values are at V
CC
=
3.3V, T
A
=
25
C.
Note 4: Applies to bushold versions only (74LVTH162240).
Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 7: This is the increase in supply current for each input that is at the specified voltage level rather than V
CC
or GND.
Dynamic Switching Characteristics
(Note 8)
Note 8: Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 9: Max number of outputs defined as (n). n
-
1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
Note 10: All typical values are at V
CC
=
3.3V, T
A
=
25
C.
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
Capacitance
(Note 12)
Note 12: Capacitance is measured at frequency f
=
1 MHz, per MIL-STD-883, Method 3012.
Symbol
Parameter
V
CC
(V)
T
A
=
-
40
C to
+
85
C
Units
Conditions
Min
Typ
Max
(Note 3)
I
CCZ
+
Power Supply Current
3.6
0.19
mA
V
CC
V
O
5.5V,
Outputs Disabled
I
CC
Increase in Power Supply Current
3.6
0.2
mA
One Input at V
CC
-
0.6V
(Note 7)
Other Inputs at V
CC
or GND
Symbol
Parameter
V
CC
(V)
T
A
=
25
C
Units
Conditions
C
L
=
50 pF,
R
L
=
500
Min
Typ
Max
V
OLP
Quiet Output Maximum Dynamic V
OL
3.3
0.8
V
(Note 9)
V
OLV
Quiet Output Minimum Dynamic V
OL
3.3
-
0.8
V
(Note 9)
Symbol
Parameter
T
A
=
-
40
C to
+
85
C, C
L
=
50 pF, R
L
=
500
Units
V
CC
=
3.3V
0.3V
V
CC
=
2.7V
Min
Typ
Max
Min
Max
(Note 10)
t
PLH
Propagation Delay Data to Output
1.0
4.0
1.0
4.8
ns
t
PHL
1.0
4.0
1.0
4.6
t
PZH
Output Enable Time
1.0
4.8
1.0
5.7
ns
t
PZL
1.0
4.9
1.0
6.1
t
PHZ
Output Disable Time
2.0
4.9
2.0
5.4
ns
t
PLZ
2.0
4.5
2.0
4.5
t
OSHL
Output to Output Skew
1.0
1.0
ns
t
OSLH
(Note 11)
Symbol
Parameter
Conditions
Typical
Units
C
IN
Input Capacitance
V
CC
=
0V, V
I
=
0V or V
CC
4
pF
C
OUT
Output Capacitance
V
CC
=
3.0V, V
O
=
0V or V
CC
8
pF
5
www.fairchildsemi.com
7
4
L
V
T1
62240
74L
VTH162240
Physical Dimensions
inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
www.fairchildsemi.com
6
74L
VT162
240
74L
VTH162240 Low
V
o
l
t
age 16-
Bit
I
nvert
i
ng Buf
f
er
/Li
ne
Dr
iver
wi
th 3-ST
A
T
E
Out
puts and 25
Ser
i
es Resis
t
ors
i
n
t
he O
u
t
puts
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
PDF 
ZIP