2005 Fairchild Semiconductor Corporation
DS012021
www.fairchildsemi.com
January 1999
Revised June 2005
7
4
L
V
T1
6373
74L
VTH16373 Low
V
o
l
t
age 16-Bi
t T
r
ansp
ar
ent Latc
h
wit
h
3-ST
A
T
E
Outp
ut
s
74LVT16373 74LVTH16373
Low Voltage 16-Bit Transparent Latch
with 3-STATE Outputs
General Description
The LVT16373 and LVTH16373 contain sixteen non-invert-
ing latches with 3-STATE outputs and is intended for bus
oriented applications. The device is byte controlled. The
flip-flops appear transparent to the data when the Latch
Enable (LE) is HIGH. When LE is LOW, the data that meets
the setup time is latched. Data appears on the bus when
the Output Enable (OE) is LOW. When OE is HIGH, the
outputs are in a high impedance state.
The LVTH16373 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These latches are designed for low-voltage (3.3V) V
CC
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVT16373 and LVTH16373
are fabricated with an advanced BiCMOS technology to
achieve high speed operation similar to 5V ABT while
maintaining a low power dissipation.
Features
s
Input and output interface capability to systems at
5V V
CC
s
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH16373),
also available without bushold feature (74LVT16373)
s
Live insertion/extraction permitted
s
Power Up/Power Down high impedance provides
glitch-free bus loading
s
Outputs source/sink
32 mA/
64 mA
s
Functionally compatible with the 74 series 16373
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human-body model
!
2000V
Machine model
!
200V
Charged-device model
!
1000V
s
Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Ordering Code:
Note 1: BGA package available in Tape and Reel only.
Note 2: Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
Order Number
Package Number
Package Description
74LVT16373GX
(Note 1)
BGA54A
(Preliminary)
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
74LVT16373MEA
(Note 2)
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVT16373MTD
(Note 2)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
74LVTH16373GX
(Note 1)
BGA54A
(Preliminary)
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
74LVTH16373MEA
(Note 2)
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LVTH16373MTD
(Note 2)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
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2
74L
VT16373
74L
VTH16373
Connection Diagrams
Pin Assignment for SSOP and TSSOP
Pin Assignment for FBGA
(Top Thru View)
Pin Descriptions
FBGA Pin Assignments
Truth Tables
H
HIGH Voltage Level
L
LOW Voltage Level
X
Immaterial
Z
HIGH Impedance
O
o
Previous output prior to HIGH-to-LOW transition of LE
Pin Names
Description
OE
n
Output Enable Input (Active LOW)
LE
n
Latch Enable Input
I
0
I
15
Inputs
O
0
O
15
3-STATE Outputs
NC
No Connect
1
2
3
4
5
6
A
O
0
NC
OE
1
LE
1
NC
I
0
B
O
2
O
1
NC
NC
I
1
I
2
C
O
4
O
3
V
CC
V
CC
I
3
I
4
D
O
6
O
5
GND
GND
I
5
I
6
E
O
8
O
7
GND
GND
I
7
I
8
F
O
10
O
9
GND
GND
I
9
I
10
G
O
12
O
11
V
CC
V
CC
I
11
I
12
H
O
14
O
13
NC
NC
I
13
I
14
J
O
15
NC
OE
2
LE
2
NC
I
15
Inputs
Outputs
LE
1
OE
1
I
0
I
7
O
0
O
7
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
O
o
Inputs
Outputs
LE
2
OE
2
I
8
I
15
O
8
O
15
X
H
X
Z
H
L
L
L
H
L
H
H
L
L
X
O
o
3
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7
4
L
V
T1
6373
74L
VTH16373
Functional Description
The LVT16373 and LVTH16373 contain sixteen D-type
latches with 3-STATE standard outputs. The device is byte
controlled with each byte functioning identically, but inde-
pendent of the other. Control pins can be shorted together
to obtain full 16-bit operation. The following description
applies to each byte. When the Latch Enable (LE
n
) input is
HIGH, data on the D
n
enters the latches. In this condition
the latches are transparent, i.e, a latch output will change
states each time its D input changes. When LE
n
is LOW,
the latches store information that was present on the D
inputs a setup time preceding the HIGH-to-LOW transition
of LE
n
. The 3-STATE standard outputs are controlled by
the Output Enable (OE
n
) input. When OE
n
is LOW, the
standard outputs are in the 2-state mode. When OE
n
is
HIGH, the standard outputs are in the high impedance
mode but this does not interfere with entering new data into
the latches.
Logic Diagrams
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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4
74L
VT16373
74L
VTH16373
Absolute Maximum Ratings
(Note 3)
Recommended Operating Conditions
Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied.
Note 4: I
O
Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol
Parameter
Value
Conditions
Units
V
CC
Supply Voltage
0.5 to
4.6
V
V
I
DC Input Voltage
0.5 to
7.0
V
V
O
DC Output Voltage
0.5 to
7.0
Output in 3-STATE
V
0.5 to
7.0
Output in HIGH or LOW State (Note 4)
I
IK
DC Input Diode Current
50
V
I
GND
mA
I
OK
DC Output Diode Current
50
V
O
GND
mA
I
O
DC Output Current
64
V
O
!
V
CC
Output at HIGH State
mA
128
V
O
!
V
CC
Output at LOW State
I
CC
DC Supply Current per Supply Pin
r
64
mA
I
GND
DC Ground Current per Ground Pin
r
128
mA
T
STG
Storage Temperature
65 to
150
q
C
Symbol
Parameter
Min
Max
Units
V
CC
Supply Voltage
2.7
3.6
V
V
I
Input Voltage
0
5.5
V
I
OH
HIGH Level Output Current
32
mA
I
OL
LOW Level Output Current
64
mA
T
A
Free-Air Operating Temperature
40
85
q
C
'
t/
'
V
Input Edge Rate, V
IN
0.8V2.0V, V
CC
3.0V
0
10
ns/V
Symbol
Parameter
V
CC
T
A
40
q
C to
85
q
C
Units
Conditions
(V)
Min
Max
V
IK
Input Clamp Diode Voltage
2.7
1.2
V
I
I
18 mA
V
IH
Input HIGH Voltage
2.73.6
2.0
V
V
O
d
0.1V or
V
IL
Input LOW Voltage
2.73.6
0.8
V
V
O
t
V
CC
0.1V
V
OH
Output HIGH Voltage
2.73.6
V
CC
0.2
V
I
OH
100
P
A
2.7
2.4
I
OH
8 mA
3.0
2.0
I
OH
32 mA
V
OL
Output LOW Voltage
2.7
0.2
V
I
OL
100
P
A
2.7
0.5
I
OL
24 mA
3.0
0.4
I
OL
16 mA
3.0
0.5
I
OL
32 mA
3.0
0.55
I
OL
64 mA
I
I(HOLD)
Bushold Input Minimum Drive
3.0
75
P
A
V
I
0.8V
(Note 5)
75
V
I
2.0V
I
I(OD)
Bushold Input Over-Drive
3.0
500
P
A
(Note 6)
(Note 5)
Current to Change State
500
(Note 7)
I
I
Input Current
3.6
10
P
A
V
I
5.5V
Control Pins
3.6
r
1
V
I
0V or V
CC
Data Pins
3.6
5
V
I
0V
1
V
I
V
CC
I
OFF
Power Off Leakage Current
0
r
100
P
A
0V
d
V
I
or V
O
d
5.5V
I
PU/PD
Power Up/Down 3-STATE
01.5V
r
100
P
A
V
O
0.5V to 3.0V
Output Current
V
I
GND or V
CC
I
OZL
3-STATE Output Leakage Current
3.6
5
P
A
V
O
0.5V
I
OZH
3-STATE Output Leakage Current
3.6
5
P
A
V
O
3.0V
I
OZH
3-STATE Output Leakage Current
3.6
10
P
A
V
CC
V
O
d
5.5V
5
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7
4
L
V
T1
6373
74L
VTH16373
DC Electrical Characteristics
(Continued)
Note 5: Applies to bushold versions only (74LVTH16373).
Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than V
CC
or GND.
Dynamic Switching Characteristics
(Note 9)
Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested.
Note 10: Max number of outputs defined as (n). n
1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
Capacitance
(Note 12)
Note 12: Capacitance is measured at frequency f
1 MHz, per MIL-STD-883, Method 3012.
Symbol
Parameter
V
CC
T
A
40
q
C to
85
q
C
Units
Conditions
(V)
Min
Max
I
CCH
Power Supply Current
3.6
0.19
mA
Outputs HIGH
I
CCL
Power Supply Current
3.6
5
mA
Outputs LOW
I
CCZ
Power Supply Current
3.6
0.19
mA
Outputs Disabled
I
CCZ
Power Supply Current
3.6
0.19
mA
V
CC
d
V
O
d
5.5V,
Outputs Disabled
'
I
CC
Increase in Power Supply Current
3.6
0.2
mA
One Input at V
CC
0.6V
(Note 8)
Other Inputs at V
CC
or GND
Symbol
Parameter
V
CC
T
A
25
q
C
Units
Conditions
(V)
Min
Typ
Max
C
L
50 pF, R
L
500
:
V
OLP
Quiet Output Maximum Dynamic V
OL
3.3
0.8
V
(Note 10)
V
OLV
Quiet Output Minimum Dynamic V
OL
3.3
0.8
V
(Note 10)
Symbol
Parameter
T
A
40
q
C to
85
q
C, C
L
50pF, R
L
500
:
Units
V
CC
3.3V
r
0.3V
V
CC
2.7V
Min
Max
Min
Max
t
PHL
Propagation Delay
1.5
3.9
1.5
4.3
ns
t
PLH
D
n
to O
n
1.5
3.8
1.5
4.2
t
PHL
Propagation Delay
1.9
4.2
1.9
4.4
ns
t
PLH
LE to O
n
1.6
4.3
1.6
4.8
t
PZL
Output Enable Time
1.3
4.3
1.3
4.9
ns
t
PZH
1.0
4.3
1.0
5.1
t
PLZ
Output Disable Time
1.5
4.7
1.5
4.8
ns
t
PHZ
2.0
5.0
2.0
5.4
t
S
Setup Time, D
n
to LE
1.0
0.8
ns
t
H
Hold Time, D
n
to LE
1.0
1.1
ns
t
W
LE Pulse Width
3.0
3.0
ns
t
OSHL
Output to Output Skew (Note 11)
1.0
1.0
ns
t
OSLH
1.0
1.0
Symbol
Parameter
Conditions
Typical
Units
C
IN
Input Capacitance
V
CC
Open, V
I
0V or V
CC
4
pF
C
OUT
Output Capacitance
V
CC
3.0V, V
O
0V or V
CC
8
pF
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