2005 Fairchild Semiconductor Corporation
DS011612
www.fairchildsemi.com
October 1993
Revised April 2005
7
4
L
VX37
4
Low V
o
l
t
age Oct
a
l D-T
ype Fl
ip-
F
lop wit
h
3-
ST
A
T
E Output
s
74LVX374
Low Voltage Octal D-Type Flip-Flop with
3-STATE Outputs
General Description
The LVX374 is a high-speed, low-power octal D-type flip-
flop featuring separate D-type inputs for each flip-flop and
3-STATE outputs for bus-oriented applications. A buffered
Clock (CP) and Output Enable (OE) are common to all flip-
flops. The inputs tolerate up to 7V allowing interface of 5V
systems to 3V systems.
Features
s
Input voltage translation from 5V to 3V
s
Ideal for low power/low noise 3.3V applications
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
Order Number
Package Number
Package Description
74LVX374M
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LVX374SJ
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX374MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names
Description
D
0
D
7
Data Inputs
CP
Clock Pulse Input
OE
3-STATE Output Enable Input
O
0
O
7
3-STATE Outputs
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74
L
VX374
Truth Table
H
HIGH Voltage Level
L
LOW Voltage Level
X
Immaterial
Z
High Impedance
LOW-to-HIGH Transition
Functional Description
The LVX374 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE true outputs. The
buffered clock and buffered Output Enable are common to
all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold time
requirements on the LOW-to-HIGH Clock (CP) transition.
With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. Opera-
tion of the OE input does not affect the state of the flip-
flops.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs
Outputs
D
n
CP
OE
O
n
H
L
H
L
L
L
X
X
H
Z
3
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L
V
X
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Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
(Note 2)
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Noise Characteristics
(Note 3)
Note 3: Input t
r
t
f
3 ns
Supply Voltage (V
CC
)
0.5V to
7.0V
DC Input Diode Current (I
IK
)
V
I
0.5V
20 mA
DC Input Voltage (V
I
)
0.5V to 7V
DC Output Diode Current (I
OK
)
V
O
0.5V
20 mA
V
O
V
CC
0.5V
20 mA
DC Output Voltage (V
O
)
0.5V to V
CC
0.5V
DC Output Source
or Sink Current (I
O
)
r
25 mA
DC V
CC
or Ground Current
(I
CC
or I
GND
)
r
75 mA
Storage Temperature (T
STG
)
65
q
C to
150
q
C
Power Dissipation
180mW
Supply Voltage (V
CC
)
2.0V to 3.6V
Input Voltage (V
I
)
0V to 5.5V
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
40
q
C to
85
q
C
Input Rise and Fall Time (
'
t/
'
V)
0 ns/V to 100 ns/V
Symbol
Parameter
V
CC
T
A
25
q
C
T
A
40
q
C to
85
q
C
Units
Conditions
Min
Typ
Max
Min
Max
V
IH
HIGH Level
2.0
1.5
1.5
Input Voltage
3.0
2.0
2.0
V
3.6
2.4
2.4
V
IL
LOW Level
2.0
0.5
0.5
Input Voltage
3.0
0.8
0.8
V
3.6
0.8
0.8
V
OH
HIGH Level
2.0
1.9
2.0
1.9
V
IN
V
IH
I
OH
50
P
A
Output Voltage
3.0
2.9
3.0
2.9
V
or V
IL
I
OH
50
P
A
3.0
2.58
2.48
I
OH
4mA
V
OL
LOW Level
2.0
0.0
0.1
0.1
V
IN
V
IH
I
OL
50
P
A
Output Voltage
3.0
0.0
0.1
0.1
V
or V
IL
I
OL
50
P
A
3.0
0.36
0.44
I
OL
4mA
I
OZ
3-STATE Output
3.6
r
0.25
r
2.5
V
IN
V
IH
or V
IL
Off-State Current
P
A
V
OUT
V
CC
or GND
I
IN
Input Leakage Current
3.6
r
0.1
r
1.0
P
A
V
IN
5.5V or GND
I
CC
Quiescent Supply Current
3.6
4.0
40.0
P
A
V
IN
V
CC
or GND
Symbol
Parameter
V
CC
T
A
25
q
C
Units
C
L
(pF)
(V)
Typ
Limit
V
OLP
Quiet Output Maximum Dynamic V
OL
3.3
0.5
0.8
V
50
V
OLV
Quiet Output Minimum Dynamic V
OL
3.3
0.5
0.8
V
50
V
IHD
Minimum HIGH Level Dynamic Input Voltage
3.3
2.0
V
50
V
ILD
Maximum LOW Level Dynamic Input Voltage
3.3
0.8
V
50
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74
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VX374
AC Electrical Characteristics
Note 4: Parameter guaranteed by design. t
OSLH
|t
PLHm
t
PLHn
|, t
OSHL
|t
PHLm
t
PHLn
|
Capacitance
Note 5: C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Symbol
Parameter
V
CC
T
A
25
q
C
T
A
40
q
C to
85
q
C
Units
Conditions
(V)
Min
Typ
Max
Min
Max
f
MAX
Maximum Clock
2.7
60
115
50
MHz
C
L
15 pF
Frequency
45
60
40
C
L
50 pF
3.3
r
0.3
100
160
85
C
L
15 pF
60
95
55
C
L
50 pF
t
PLH
Propagation Delay Time
2.7
8.5
16.3
1.0
19.5
ns
C
L
15 pF
t
PHL
CP to O
n
11.0
19.8
1.0
23.0
C
L
50 pF
3.3
r
0.3
6.7
10.6
1.0
12.5
C
L
15 pF
9.2
14.1
1.0
16.0
C
L
50 pF
t
PZL
3-STATE Output
2.7
7.6
14.5
1.0
17.5
ns
C
L
15 pF, R
L
1 k
:
t
PZH
Enable Time
10.1
18.0
1.0
21.0
C
L
50 pF, R
L
1 k
:
3.3
r
0.3
5.9
9.3
1.0
11.0
C
L
15 pF, R
L
1 k
:
8.4
12.8
1.0
14.5
C
L
50 pF, R
L
1 k
:
t
PLZ
3-STATE Output
2.7
11.5
18.5
1.0
22.0
ns
C
L
50 pF, R
L
1 k
:
t
PHZ
Disable Time
3.3
r
0.3
9.6
13.2
1.0
15.0
C
L
50 pF, R
L
1 k
:
t
W
CP Pulse
2.7
7.5
8.0
ns
Width
3.3
r
0.3
5.0
5.5
t
S
Setup Time
2.7
6.5
6.5
ns
D
n
to CP
3.3
r
0.3
4.5
4.5
t
H
Hold Time
2.7
2.0
2.0
ns
D
n
to CP
3.3
r
0.3
2.0
2.0
t
OSLH
Output to Output
2.7
1.5
1.5
ns
C
L
50 pF
t
OSHL
Skew (Note 4)
3.3
1.5
1.5
Symbol
Parameter
T
A
25
q
C
T
A
40
q
C to
85
q
C
Units
Min
Typ
Max
Min
Max
C
IN
Input Capacitance
4
10
10
pF
C
OUT
Output Capacitance
6
pF
C
PD
Power Dissipation
32
pF
Capacitance (Note 5)
5
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74
L
V
X
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74
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
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