2003 Fairchild Semiconductor Corporation
DS012009
www.fairchildsemi.com
February 1994
Revised October 2003
7
4
L
VXC424
5 8-
Bit
Dual
Supp
ly
Confi
gurabl
e
V
o
l
t
a
g
e I
n
ter
f
ac
e T
r
anscei
ver
wit
h
3-
ST
A
T
E
Output
s
74LVXC4245
8-Bit Dual Supply Configurable Voltage Interface
Transceiver with 3-STATE Outputs
General Description
The LVXC4245 is a 24-pin dual-supply, 8-bit configurable
voltage interface transceiver suited for PCMCIA and other
real time configurable I/O applications. The V
CCA
pin
accepts a 5V supply level. The "A" Port is a dedicated 5V
port. The V
CCB
pin accepts a 3V-to-5V supply level. The
"B" Port is configured to track the V
CCB
supply level
respectively. A 5V level on the V
CC
pin will configure the
I/O pins at a 5V level and a 3V V
CC
will configure the I/O
pins at a 3V level. This device will allow the V
CCB
voltage
source pin and I/O pins on the "B" Port to float when OE is
HIGH. This feature is necessary to buffer data to and from
a PCMCIA socket that permits PCMCIA cards to be
inserted and removed during normal operation.
Features
s
Bidirectional interface between 5V and 3V-to-5V buses
s
Control inputs compatible with TTL level
s
Outputs source/sink up to 24 mA
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Implements patented EMI reduction circuitry
s
Flexible V
CCB
operating range
s
Allows B Port and V
CCB
to float simultaneously when OE
is HIGH
s
Functionally compatible with the 74 series 245
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
Pin Descriptions
Connection Diagram
Order Number
Package Number
Package Description
74LVXC4245WM
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LVXC4245QSC
MQA24
24-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
74LVXC4245MTC
MTC24
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names
Description
OE
Output Enable Input
T/R
Transmit/Receive Input
A
0
A
7
Side A Inputs or 3-STATE Outputs
B
0
B
7
Side B Inputs or 3-STATE Outputs
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74
L
VXC4245
Truth Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Logic Diagram
Inputs
Outputs
OE
T/R
L
L
Bus B Data to Bus A
L
H
Bus A Data to Bus B
H
X
HIGH-Z State
3
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VXC424
5
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
(Note 2)
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Note 2: The A Port unused pins (inputs and I/O's) must be held HIGH or
LOW. They may not float.
DC Electrical Characteristics
Supply Voltage (V
CCA
,V
CCB
)
-
0.5V to
+
7.0V
DC Input Voltage (V
I
) @ OE, T/R
-
0.5V to V
CCA
+
0.5V
DC Input/Output Voltage (V
I/O
)
@ A
n
-
0.5V to V
CCA
+
0.5V
@ B
n
-
0.5V to V
CCB
+
0.5V
DC Input Diode Current (I
IK
)
@ OE, T/R
20 mA
DC Output Diode Current (I
OK
)
50 mA
DC Output Source or
Sink Current (I
O
)
50 mA
DC V
CC
or Ground Current
Per Output Pin (I
CC
or I
GND
)
50 mA
and Max Current
200 mA
Storage Temperature Range (T
STG
)
-
65
C to
+
150
C
DC Latch-Up Source or
Sink Current
300 mA
Supply Voltage
V
CCA
4.5V to 5.5V
V
CCB
2.7V to 5.5V
Input Voltage (V
I
) @ OE, T/R
0V to V
CCA
Input/Output Voltage (V
I/O
)
@A
n
0V to V
CCA
@B
n
0V to V
CCB
Free Air Operating Temperature (T
A
)
-
40
C to
+
85
C
Minimum Input Edge Rate (
V/
t)
8 ns/V
V
IN
from 30% to 70% of V
CC
V
CC
@ 3V, 4.5V, 5.5V
Symbol
Parameter
V
CCA
V
CCB
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
(V)
(V)
Typ
Guaranteed Limits
V
IHA
Minimum HIGH Level
A
n
4.5
2.7
2.0
2.0
V
V
OUT
0.1V
Input Voltage
OE
4.5
3.6
2.0
2.0
or
T/R
5.5
5.5
2.0
2.0
V
CC
-
0.1V
V
IHB
B
n
4.5
2.7
2.0
2.0
4.5
3.6
2.0
2.0
4.5
5.5
3.85
3.85
V
ILA
Maximum LOW Level
A
n
4.5
2.7
0.8
0.8
V
V
OUT
0.1V
Input Voltage
OE
4.5
3.6
0.8
0.8
or
T/R
5.5
5.5
0.8
0.8
V
CC
-
0.1V
V
ILB
B
n
4.5
2.7
0.8
0.8
4.5
3.6
0.8
0.8
4.5
5.5
1.65
1.65
V
OHA
Minimum HIGH Level
4.5
3.0
4.49
4.4
4.4
V
I
OUT
=
-
100
A
Output Voltage
4.5
3.0
4.25
3.86
3.76
I
OH
=
-
24 mA
V
OHB
4.5
3.0
2.99
2.9
2.9
V
I
OUT
=
-
100
A
4.5
3.0
2.85
2.56
2.46
I
OH
=
-
12 mA
4.5
3.0
2.65
2.35
2.25
I
OH
=
-
24 mA
4.5
2.7
2.5
2.3
2.2
I
OH
=
-
12 mA
4.5
2.7
2.3
2.1
2.0
I
OH
=
-
24 mA
4.5
4.5
4.25
3.86
3.76
I
OH
=
-
24 mA
V
OLA
Maximum LOW Level
4.5
3.0
0.002
0.1
0.1
V
I
OUT
=
100
A
Output Voltage
4.5
3.0
0.21
0.36
0.44
I
OL
=
24 mA
V
OLB
4.5
3.0
0.002
0.1
0.1
V
I
OUT
=
100
A
4.5
3.0
0.21
0.36
0.44
I
OL
=
24 mA
4.5
2.7
0.11
0.36
0.44
I
OL
=
12 mA
4.5
2.7
0.22
0.42
0.5
I
OL
=
24 mA
4.5
4.5
0.18
0.36
0.44
I
OL
=
24 mA
I
IN
Maximum Input
V
I
=
V
CCA
, GND
Leakage Current @
5.5
3.6
0.1
1.0
A
OE, T/R
5.5
5.5
0.1
1.0
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74
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VXC4245
DC Electrical Characteristics
(Continued)
Note 3: Worst case package.
Note 4: Max number of outputs defined as (n). Data inputs are driven 0V to V
CC
level; one output at GND.
Note 5: Max number of Data Inputs (n) switching. (n
-
1) inputs switching 0V to V
CC
level. Input-under-test switching:
V
CC
level to threshold (V
IHD
), 0V to threshold (V
ILD
), f
=
1 MHz.
Symbol
Parameter
V
CCA
V
CCB
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
(V)
(V)
Typ
Guaranteed Limits
I
OZA
Maximum 3-STATE
5.5
3.6
0.5
5.0
A
V
I
=
V
IL
, V
IH
, OE
=
V
CCA
Output Leakage @ A
n
5.5
5.5
0.5
5.0
V
O
=
V
CCA
, GND
I
OZB
Maximum 3-STATE
5.5
3.6
0.5
5.0
A
V
I
=
V
IL
, V
IH
, OE
=
V
CCA
Output Leakage @ B
n
5.5
5.5
0.5
5.0
V
O
=
V
CCB
, GND
I
CC
Maximum All
Inputs
5.5
5.5
1.0
1.35
1.5
mA
V
I
=
V
CC
-
2.1V
I
CC
/Input
B
n
5.5
3.6
0.35
0.5
mA
V
I
=
V
CCB
-
0.6V
I
CCA1
Quiescent V
CCA
A
n
=
V
CCA
or GND
Supply Current as B
5.5
Open
8
80
A
B
n
=
Open, OE
=
V
CCA
Port Floats
T/R
=
V
CCA
, V
CCB
=
Open
I
CCA2
Quiescent V
CCA
A
n
=
V
CCA
or GND
Supply Current
5.5
3.6
8
80
A
B
n
=
V
CCB
or GND
5.5
5.5
8
80
OE
=
GND, T/R
=
GND
I
CCB
Quiescent V
CCB
A
n
=
V
CCA
or GND
Supply Current
5.5
3.6
5
50
A
B
n
=
V
CCB
or GND
5.5
5.5
8
80
OE
=
GND, T/R
=
V
CCA
V
OLPA
Quiet Output
5.0
3.3
1.5
V
(Note 3) (Note 4)
Maximum Dynamic
5.0
5.0
1.5
V
OLPB
V
OL
5.0
3.3
0.8
V
(Note 3) (Note 4)
5.0
5.0
1.5
V
OLVA
Quiet Output Minimum
5.0
3.3
-
1.2
V
(Note 3) (Note 4)
Dynamic V
OL
5.0
5.0
-
1.2
V
OLVB
5.0
3.3
-
0.8
V
(Note 3) (Note 4)
5.0
5.0
-
1.2
V
IHDA
Minimum HIGH Level
5.0
3.3
2.0
V
(Note 3) (Note 5)
Dynamic Input
5.0
5.0
2.0
V
IHDB
Voltage
5.0
3.3
2.0
V
(Note 3) (Note 5)
5.0
5.0
3.5
V
ILDA
Maximum LOW Level
5.0
3.3
0.8
V
(Note 3) (Note 5)
Dynamic Input
5.0
5.0
0.8
V
ILDB
Voltage
5.0
3.3
0.8
V
(Note 3) (Note 5)
5.0
5.0
1.5
5
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VXC424
5
AC Electrical Characteristics
Note 6: Typical values at V
CCA
=
5V, V
CCB
=
5V @25
C.
Note 7: Typical values at V
CCA
=
5V, V
CCB
=
3.3V @25
C.
Note 8: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
). Parameter guaranteed by design.
Capacitance
Note 9: C
PD
is measured at 10 MHz.
Power Up Considerations
To insure the system does not experience unnecessary I
CC
current draw, bus contention, or oscillations during power
up, the following guidelines should be adhered to (refer to
Table 1):
Power up the control side of the device first. This is the
V
CCA
.
OE should ramp with or ahead of V
CCA
. This will help
guard against bus contention.
The Transmit/Receive control pin (T/R) should ramp with
V
CCA
, this will ensure that the A Port data pins are con-
figured as inputs. With V
CCA
receiving power first, the A
I/O Port should be configured as inputs to help guard
against bus contention and oscillations.
A side data inputs should be driven to a valid logic level.
This will prevent excessive current draw.
The above steps will ensure that no bus contention or oscil-
lations, and therefore no excessive current draw occurs
during the power up cycling of these devices. These steps
will help prevent possible damage to the translator devices
and potential damage to other system components.
TABLE 1. Low Voltage Translator Power Up Sequencing Table
Please reference Application Note AN-5001 for more detailed information on using Fairchild's LVX Low Voltage Dual
Supply CMOS Translating Transceivers.
Symbol
Parameter
C
L
=
50 pF
C
L
=
50 pF
Units
V
CCA
=
4.5V to 5.5V
V
CCA
=
4.5V to 5.5V
V
CCB
=
4.5V to 5.5V
V
CCB
=
2.7V to 3.6V
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Min
Typ
Max
Min
Max
Min
Typ
Max
Min
Max
(Note 6)
(Note 7)
t
PHL
Propagation
1.0
4.9
6.5
1.0
7.0
1.0
5.5
7.5
1.0
8.0
ns
t
PLH
Delay A to B
1.0
4.0
5.5
1.0
6.0
1.0
5.0
7.0
1.0
7.5
t
PHL
Propagation
1.0
4.7
6.5
1.0
7.0
1.0
5.6
7.5
1.0
8.0
ns
t
PLH
Delay B to A
1.0
3.9
5.0
1.0
5.5
1.0
4.3
6.0
1.0
6.5
t
PZL
Output Enable
1.0
5.6
7.5
1.0
8.0
1.0
6.7
9.0
1.0
10.0
ns
t
PZH
Time OE to B
1.0
5.7
7.5
1.0
8.0
1.0
6.9
9.5
1.0
10.0
t
PZL
Output Enable
1.0
7.4
9.0
1.0
10.0
1.0
8.0
10.0
1.0
11.0
ns
t
PZH
Time OE to A
1.0
6.1
7.5
1.0
8.5
1.0
6.3
8.0
1.0
8.5
t
PHZ
Output Disable
1.0
4.8
7.0
1.0
7.5
1.0
6.0
9.0
1.0
9.5
ns
t
PLZ
Time OE to B
1.0
3.8
5.5
1.0
6.0
1.0
4.2
6.5
1.0
7.0
t
PHZ
Output Disable
1.0
3.4
5.5
1.0
6.0
1.0
3.4
5.5
1.0
6.0
ns
t
PLZ
Time OE to A
1.0
2.9
4.5
1.0
5.0
1.0
2.9
5.0
1.0
5.5
t
OSHL
Output to Output
t
OSLH
Skew (Note 8)
1.0
1.5
1.5
1.0
1.5
1.5
ns
Data to Output
Symbol
Parameter
Typ
Units
Conditions
C
IN
Input Capacitance
4.5
pF
V
CC
=
Open
C
I/O
Input/Output Capacitance
10
pF
V
CCA
=
5V, V
CCB
=
3.3V
C
PD
Power Dissipation Capacitance
A
B
45
pF
V
CCA
=
5V
(Note 9)
B
A
50
pF
V
CCB
=
3.3V
Device Type
V
CCA
V
CCB
T/R
OE
A Side I/O
B Side I/O
Floatable Pin
Allowed
74LVXC4245
5V
2.7V to 5.5V
ramp
ramp
logic
outputs
yes, V
CCB
and B
(power up 1st)
configurable
with V
CCA
with V
CCA
0V or V
CCA
I/O's w/ OE HIGH
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