August 1993
Revised March 1999
7
4
VH
C12
5
Quad Buff
er w
i
t
h
3-
ST
A
T
E O
u
tput
s
1999 Fairchild Semiconductor Corporation
DS011632.prf
www.fairchildsemi.com
74VHC125
Quad Buffer with 3-STATE Outputs
General Description
The VHC125 contains four independent non-inverting buff-
ers with 3-STATE outputs. It is an advanced high-speed
CMOS device fabricated with silicon gate CMOS technol-
ogy and achieves the high-speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
An input protection circuit insures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
s
High Speed: t
PD
=
3.8 ns (typ) at V
CC
=
5V
s
Lower power dissipation: I
CC
=
4
A (max) at T
A
=
25
C
s
High noise immunity: V
NIH
=
V
NIL
=
28% V
CC
(min)
s
Power down protection is provided on all inputs
s
Low noise: V
OLP
=
0.8V (max)
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
IEEE/IEC
Pin Descriptions
Connection Diagram
Function Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
Z
=
HIGH Impedance
X
=
Immaterial
Order Number
Package Number
Package Description
74VHC125M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74VHC125SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC125MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC125N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names
Description
A
n
, B
n
Inputs
O
n
Outputs
Inputs
Output
A
n
B
n
O
n
L
L
L
L
H
H
H
X
Z
www.fairchildsemi.com
2
74
V
HC125
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
(Note 2)
Note 1: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Noise Characteristics
Note 3: Parameter guaranteed by design.
Supply Voltage (V
CC
)
-
0.5V to
+
7.0V
DC Input Voltage (V
IN
)
-
0.5V to
+
7.0V
DC Output Voltage (V
OUT
)
-
0.5V to V
CC
+
0.5V
Input Diode Current (I
IK
)
-
20 mA
Output Diode Current (I
OK
)
20 mA
DC Output Current (I
OUT
)
25 mA
DC V
CC
/GND Current (I
CC
)
50 mA
Storage Temperature (T
STG
)
-
65
C to
+
150
C
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
C
Supply Voltage (V
CC
)
2.0V to
+
5.5V
Input Voltage (V
IN
)
0V to
+
5.5V
Output Voltage (V
OUT
)
0V to V
CC
Operating Temperature (T
OPR
)
-
40
C to
+
85
C
Input Rise and Fall Time (t
r
, t
f
)
V
CC
=
3.3V
0.3V
0
100 ns/V
V
CC
=
5.0V
0.5V
0
20 ns/V
Symbol
Parameter
V
CC
(V)
T
A
=
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
Min
Typ
Max
Min
Max
V
IH
HIGH Level Input
2.0
1.50
1.50
V
Voltage
3.0
-
5.5
0.7 V
CC
0.7 V
CC
V
IL
LOW Level Input
2.0
0.50
0.50
V
Voltage
3.0
-
5.5
0.3 V
CC
0.3 V
CC
V
OH
HIGH Level Output
2.0
1.9
2.0
1.9
V
IN
=
V
IH
I
OH
=
-
50
A
Voltage
3.0
2.9
3.0
2.9
V
or V
IL
4.5
4.4
4.5
4.4
3.0
2.58
2.48
V
I
OH
=
-
4 mA
4.5
3.94
3.80
I
OH
=
-
8 mA
V
OL
LOW Level Output
2.0
0.0
0.1
0.1
V
IN
=
V
IH
I
OL
=
50
A
Voltage
3.0
0.0
0.1
0.1
V
or V
IL
4.5
0.0
0.1
0.1
3.0
0.36
0.44
V
I
OL
=
4 mA
4.5
0.36
0.44
I
OL
=
8 mA
I
OZ
3-STATE Output
5.5
0.25
2.5
A
V
IN
=
V
IH
or V
IL
Off-State Current
V
OUT
=
V
CC
or GND
I
IN
Input Leakage
0
-
5.5
0.1
1.0
A
V
IN
=
5.5V or GND
Current
I
CC
Quiescent Supply
5.5
4.0
40.0
A
V
IN
=
V
CC
or GND
Current
Symbol
Parameter
V
CC
(V)
T
A
=
25
C
Units
Conditions
Typ
Limits
V
OLP
Quiet Output Maximum
5.0
0.5
0.8
V
C
L
=
50 pF
(Note 3)
Dynamic V
OL
V
OLV
Quiet Output Minimum
5.0
-
0.5
-
0.8
V
C
L
=
50 pF
(Note 3)
Dynamic V
OL
V
IHD
Minimum HIGH Level
5.0
3.5
V
C
L
=
50 pF
(Note 3)
Dynamic Input Voltage
V
ILD
Maximum HIGH Level
5.0
1.5
V
C
L
=
50 pF
(Note 3)
Dynamic Input Voltage
3
www.fairchildsemi.com
7
4
VH
C12
5
AC Electrical Characteristics
Note 4: Parameter guaranteed by design. t
OSLH
=
|t
PLHmax
-
t
PLHmin
|; t
OSHL
=
|t
PHLmax
-
t
PHLmin
|.
Note 5: C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained by the equation: I
CC
(OPR.)
=
C
PD
* V
CC
* f
IN
+
I
CC
/4 (per bit).
Symbol
Parameter
V
CC
(V)
T
A
=
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay
3.3
0.3
5.6
8.0
1.0
9.5
ns
C
L
=
15 pF
t
PHL
Time
8.1
11.5
1.0
13.0
C
L
=
50 pF
5.0
0.5
3.8
5.5
1.0
6.5
ns
C
L
=
15 pF
5.3
7.5
1.0
8.5
C
L
=
50 pF
t
PZL
3-STATE Output
3.3
0.3
5.4
8.0
1.0
9.5
ns
R
L
=
1 k
C
L
=
15 pF
t
PZH
Enable Time
7.9
11.5
1.0
13.0
C
L
=
50 pF
5.0
0.5
3.6
5.1
1.0
6.0
ns
C
L
=
15 pF
5.1
7.1
1.0
8.0
C
L
=
50 pF
t
PLZ
3-STATE Output
3.3
0.3
9.5
13.2
1.0
15.0
ns
R
L
=
1 k
C
L
=
50 pF
t
PHZ
Disable Time
5.0
0.5
6.1
8.8
1.0
10.0
C
L
=
50 pF
t
OSLH
Output to Output Skew
3.3
0.3
1.5
1.5
ns
(Note 4)
C
L
=
50 pF
t
OSHL
5.0
0.5
1.0
1.0
C
L
=
50 pF
C
IN
Input Capacitance
4
10
10
pF
V
CC
=
Open
C
OUT
Output Capacitance
6
pF
V
CC
=
5.0V
C
PD
Power Dissipation
14
pF
(Note 5)
Capacitance
www.fairchildsemi.com
4
74
V
HC125
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
5
www.fairchildsemi.com
7
4
VH
C12
5
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
PDF 
ZIP