August 1993
Revised April 1999
7
4
VH
C17
5
Quad D-T
ype Fli
p
-F
lop
1999 Fairchild Semiconductor Corporation
DS011637.prf
www.fairchildsemi.com
74VHC175
Quad D-Type Flip-Flop
General Description
The VHC175 is an advanced high-speed CMOS device
fabricated with silicon gate CMOS technology. It achieves
the high-speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi-
pation.
The VHC175 is a high-speed quad D-type flip-flop. The
device is useful for general flip-flop requirements where
clock and clear inputs are common. The information on the
D inputs is stored during the LOW-to-HIGH clock transition.
Both true and complemented outputs of each flip-flop are
provided. A Master Reset input resets all flip-flops, inde-
pendent of the Clock or D inputs, when LOW.
An input protection circuit insures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
s
High Speed: f
MAX
=
210 MHz (typ) at V
CC
=
5V
s
Low power dissipation: I
CC
=
4
A (max) at T
A
=
25
C
s
High noise immunity: V
NIH
=
V
NIL
=
28% V
CC
(min)
s
Power down protection is provided on all inputs
s
Low noise: V
OLP
=
0.8V (max)
s
Pin and function compatible with 74HC175
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Descriptions
Logic Symbols
IEEE/IEC
Order Number
Package Number
Package Description
74VHC175M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74VHC175SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC175MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC175N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names
Description
D
0
D
3
Data Inputs
CP
Clock Pulse Input
MR
Master Reset Input
Q
0
Q
3
True Outputs
Q
0
Q
3
Complement Outputs
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2
74
V
HC175
Functional Description
The VHC175 consists of four edge-triggered D flip-flops
with individual D inputs and Q and Q outputs. The Clock
and Master Reset are common. The four flip-flops will store
the state of their individual D inputs on the LOW-to-HIGH
clock (CP) transition, causing individual Q and Q outputs to
follow. A LOW input on the Master Reset (MR) will force all
Q outputs LOW and Q outputs HIGH independent of Clock
or Data inputs. The VHC175 is useful for general logic
applications where a common Master Reset and Clock are
acceptable.
Truth Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
t
n
=
Bit Time before Clock Pulse
t
n
+
1
=
Bit Time after Clock Pulse
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs
Outputs
@ t
n
, MR
=
H
@ t
n
+
1
D
n
Q
n
Q
n
L
L
H
H
H
L
3
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7
4
VH
C17
5
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
(Note 2)
Note 1: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Noise Characteristics
Note 3: Parameter guaranteed by design.
Supply Voltage (V
CC
)
-
0.5V to
+
7.0V
DC Input Voltage (V
IN
)
-
0.5V to
+
7.0V
DC Output Voltage (V
OUT
)
-
0.5V to V
CC
+
0.5V
Input Diode Current (I
IK
)
-
20 mA
Output Diode Current (I
OK
)
20 mA
DC Output Current (I
OUT
)
25 mA
DC V
CC
/GND Current (I
CC
)
50 mA
Storage Temperature (T
STG
)
-
65
C to
+
150
C
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
C
Supply Voltage (V
CC
)
2.0V to
+
5.5V
Input Voltage (V
IN
)
0V to
+
5.5V
Output Voltage (V
OUT
)
0V to V
CC
Operating Temperature (T
OPR
)
-
40
C to
+
85
C
Input Rise and Fall Time (t
r
, t
f
)
V
CC
=
3.3V
0.3V
0
100 ns/V
V
CC
=
5.0V
0.5V
0
20 ns/V
Symbol
Parameter
V
CC
(V)
T
A
=
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
Min
Typ
Max
Min
Max
V
IH
HIGH Level Input
2.0
1.50
1.50
V
Voltage
3.0
-
5.5
0.7 V
CC
0.7 V
CC
V
IL
LOW Level Input
2.0
0.50
0.50
V
Voltage
3.0
-
5.5
0.3 V
CC
0.3 V
CC
V
OH
HIGH Level Output
2.0
1.9
2.0
1.9
V
V
IN
=
V
IH
I
OH
=
-
50
A
Voltage
3.0
2.9
3.0
2.9
or V
IL
4.5
4.4
4.5
4.4
3.0
2.58
2.48
V
I
OH
=
-
4 mA
4.5
3.94
3.80
I
OH
=
-
8 mA
V
OL
LOW Level Output
2.0
0.0
0.1
0.1
V
V
IN
=
V
IH
I
OL
=
50
A
Voltage
3.0
0.0
0.1
0.1
or V
IL
4.5
0.0
0.1
0.1
3.0
0.36
0.44
V
I
OL
=
4 mA
4.5
0.36
0.44
I
OL
=
8 mA
I
IN
Input Leakage Current
0
-
5.5
0.1
1.0
A
V
IN
=
5.5V or GND
I
CC
Quiescent Supply Current
5.5
4.0
40.0
A
V
IN
=
V
CC
or GND
Symbol
Parameter
V
CC
(V)
T
A
=
25
C
Units
Conditions
Typ
Limits
V
OLP
(Note 3)
Quiet Output Maximum Dynamic V
OL
5.0
0.4
0.8
V
C
L
=
50 pF
V
OLV
(Note 3)
Quiet Output Minimum Dynamic V
OL
5.0
-
0.4
-
0.8
V
C
L
=
50 pF
V
IHD
(Note 3)
Minimum HIGH Level Dynamic Input Voltage
5.0
3.5
V
C
L
=
50 pF
V
ILD
(Note 3)
Maximum LOW Level Dynamic Input Voltage
5.0
1.5
V
C
L
=
50 pF
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4
74
V
HC175
AC Electrical Characteristics
Note 4: Parameter guaranteed by design. t
OSLH
=
|t
PLHmax
-
t
PLHmin
|; t
OSHL
=
| t
PHLmax
-
t
PHLmin
|.
Note 5: C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained from the equation: I
CC
(opr.)
=
C
PD
* V
CC
* f
IN
+
I
CC
/4 (per F/F), and the total C
PD
when n pcs of the Flip-Flop operate can
be calculated by the following equation: C
PD
(total)
=
30
+
14 n
AC Operating Requirements
Note 6: V
CC
is 3.3
0.3V or 5.0
0.5V
Symbol
Parameter
V
CC
(V)
T
A
=
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
Min
Typ
Max
Min
Max
f
MAX
Maximum Clock
3.3
0.3
90
140
75
MHz
C
L
=
15 pF
Frequency
50
75
45
C
L
=
50 pF
5.0
0.5
150
210
125
MHz
C
L
=
15 pF
85
115
75
C
L
=
50 pF
t
PLH
Propagation Delay
3.3
0.3
7.5
11.5
1.0
13.5
ns
C
L
=
15 pF
t
PHL
Time (CP to Q
n
or Q
n
)
10.0
15.0
1.0
17.0
C
L
=
50 pF
5.0
0.5
4.8
7.3
1.0
8.5
ns
C
L
=
15 pF
6.3
9.3
1.0
10.5
C
L
=
50 pF
t
PLH
Propagation Delay Time
3.3
0.3
6.3
10.1
1.0
12.0
ns
C
L
=
15 pF
t
PHL
(MR to Q
n
or Q
n
)
8.8
13.6
1.0
15.5
C
L
=
50 pF
5.0
0.5
4.3
6.4
1.0
7.5
ns
C
L
=
15 pF
5.8
8.4
1.0
9.5
C
L
=
50 pF
t
OSLH
Output to
3.3
0.3
1.5
1.5
C
L
=
50 pF
t
OSHL
Output Skew
5.0
0.5
1.0
1.0
C
L
=
50 pF
(Note 4)
C
IN
Input Capacitance
4
10
10
pF
V
CC
=
Open
C
PD
Power Dissipation
44
pF
(Note 5)
Capacitance
Symbol
Parameter
V
CC
(V)
(Note 6)
T
A
=
25
C
T
A
=
-
40
C to
+
85
C
Units
Typ
Guaranteed Minimum
t
W
(L)
Minimum Pulse Width (CP)
3.3
5.0
5.0
ns
t
W
(H)
5.0
5.0
5.0
t
W
(L)
Minimum Pulse Width (MR)
3.3
5.0
5.0
ns
5.0
5.0
5.0
t
S
Minimum Setup Time (Dn to CP)
3.3
5.0
5.0
ns
5.0
4.0
4.0
t
H
Minimum Hold Time (Dn to CP)
3.3
1.0
1.0
ns
5.0
1.0
1.0
t
REC
Minimum Removal Time (MR)
3.3
5.0
5.0
ns
5.0
5.0
5.0
5
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7
4
VH
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5
Physical Dimensions
inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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