2005 Fairchild Semiconductor Corporation
DS011538
www.fairchildsemi.com
November 1992
Revised April 2005
7
4
VH
C37
4
Oct
a
l
D-
T
ype Fl
ip
-Fl
op wi
th
3-ST
A
T
E Out
put
s
74VHC374
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The VHC374 is an advanced high speed CMOS octal flip-
flop with 3-STATE output fabricated with silicon gate CMOS
technology. It achieves the high speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation. This 8-bit D-type flip-flop is
controlled by a clock input (CP) and an output enable input
(OE). When the OE input is HIGH, the eight outputs are in
a HIGH impedance state.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery back up. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
s
High Speed: t
PD
5.4 ns (typ) at V
CC
5V
s
High noise immunity: V
NIH
V
NIL
28% V
CC
(Min)
s
Power down protection is provided on all inputs
s
Low power dissipation: I
CC
4
P
A (Max) @ T
A
25
q
C
s
Pin and function compatible with 74HC374
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
IEEE/IEC
Connection Diagram
Order Number
Package Number
Package Description
74VHC374M
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74VHC374SJ
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC374MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC374N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
www.fairchildsemi.com
2
74
V
HC374
Pin Descriptions
Truth Table
H
HIGH Voltage Level
L
LOW Voltage Level
X
Immaterial
Z
High Impedance
LOW-to-HIGH Transition
Functional Description
The VHC374 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE true outputs. The
buffered clock and buffered Output Enable are common to
all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold time
requirements on the LOW-to-HIGH Clock (CP) transition.
With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. Opera-
tion of the OE input does not affect the state of the flip-
flops.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names
Description
D
0
D
7
Data Inputs
CP
Clock Pulse Input
OE
3-STATE Output Enable Input
O
0
O
7
3-STATE Outputs
Inputs
Outputs
D
n
CP
OE
O
n
H
L
H
L
L
L
X
X
H
Z
3
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7
4
VH
C37
4
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
(Note 2)
Note 1: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Noise Characteristics
Note 3: Parameter guaranteed by design.
AC Electrical Characteristics
Supply Voltage (V
CC
)
0.5V to
7.0V
DC Input Voltage (V
IN
)
0.5V to
7.0V
DC Output Voltage (V
OUT
)
0.5V to V
CC
0.5V
Input Diode Current (I
IK
)
20 mA
Output Diode Current
r
20 mA
DC Output Current (I
OUT
)
r
25 mA
DC V
CC
/GND Current (I
CC
)
r
75 mA
Storage Temperature (T
STG
)
65
q
C to
150
q
C
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
q
C
Supply Voltage (V
CC
)
2.0V to
5.5V
Input Voltage (V
IN
)
0V to
5.5V
Output Voltage (V
OUT
)
0V to V
CC
Operating Temperature (T
OPR
)
40
q
C to
85
q
C
Input Rise and Fall Time (t
r
, t
f
)
V
CC
3.3V
r
0.3V
0 ns/V 100 ns/V
V
CC
5.0V
r
0.5V
0 ns/V 20 ns/V
Symbol
Parameter
V
CC
T
A
25
q
C
T
A
40
q
C to
85
q
C
Units
Conditions
(V)
Min
Typ
Max
Min
Max
V
IH
HIGH Level Input
2.0
1.50
1.50
V
Voltage
3.0
5.5
0.7 V
CC
0.7 V
CC
V
IL
LOW Level Input Voltage
2.0
0.50
0.50
V
3.0
5.5
0.3 V
CC
0.3 V
CC
V
OH
HIGH Level Output
2.0
1.9
2.0
1.9
V
IN
V
IH
I
OH
50
P
A
Voltage
3.0
2.9
3.0
2.9
V
or V
IL
4.5
4.4
4.5
4.4
3.0
2.58
2.48
V
I
OH
4 mA
4.5
3.94
3.80
I
OH
8 mA
V
OL
LOW Level Output
2.0
0.0
0.1
0.1
V
IN
V
IH
I
OL
50
P
A
Voltage
3.0
0.0
0.1
0.1
V
or V
IL
4.5
0.0
0.1
0.1
3.0
0.36
0.44
V
I
OL
4 mA
4.5
0.36
0.44
I
OL
8 mA
I
OZ
3-STATE Output
5.5
r
0.25
r
2.5
P
A
V
IN
V
IH
or V
IL
Off-State Current
V
OUT
V
CC
or GND
I
IN
Input Leakage Current
0
5.5
r
0.1
r
1.0
P
A
V
IN
5.5V or GND
I
CC
Quiescent Supply Current
5.5
4.0
40.0
P
A
V
IN
V
CC
or GND
Symbol
Parameter
V
CC
T
A
25
q
C
Units
Conditions
(V)
Typ
Limits
V
OLP
(Note 3)
Quiet Output Maximum Dynamic V
OL
5.0
0.6
0.9
V
C
L
50 pF
V
OLV
(Note 3)
Quiet Output Minimum Dynamic V
OL
5.0
0.6
0.9
V
C
L
50 pF
V
IHD
(Note 3)
Minimum HIGH Level Dynamic Input Voltage
5.0
3.5
V
C
L
50 pF
V
ILD
(Note 3)
Maximum LOW Level Dynamic Input Voltage
5.0
1.5
V
C
L
50 pF
Symbol
Parameter
V
CC
T
A
25
q
C
T
A
40
q
C to
85
q
C
Units
Conditions
(V)
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay Time
3.3
r
0.3
8.1
12.7
1.0
15.0
ns
C
L
15 pF
t
PHL
(CP to O
n
)
10.6
16.2
1.0
18.5
C
L
50 pF
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4
74
V
HC374
AC Electrical Characteristics
(Continued)
Note 4: Parameter guaranteed by design. t
OSLH
|t
PLH max
t
PLH min
|; t
OSHL
|t
PHL max
t
PHL min
|
Note 5: C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained by the equation: I
CC
(opr.)
C
PD
* V
CC
* f
IN
I
CC
/8 (per F/F). The total C
PD
when n pcs. of the Octal D Flip-Flop operates
can be calculated by the equation: C
PD
(total)
20
12n.
AC Operating Requirements
Symbol
Parameter
V
CC
T
A
25
q
C
T
A
40
q
C to
85
q
C
Units
Conditions
(V)
Min
Typ
Max
Min
Max
5.0
r
0.5
5.4
8.1
1.0
9.5
ns
C
L
15 pF
6.9
10.1
1.0
11.5
C
L
50 pF
t
PZL
3-STATE Output
3.3
r
0.3
7.1
11.0
1.0
13.0
ns
R
L
1 k
:
C
L
15 pF
t
PZH
Enable Time
9.6
14.5
1.0
16.5
C
L
50 pF
5.0
r
0.5
5.1
7.6
1.0
9.0
ns
C
L
15 pF
6.6
9.6
1.0
11.0
C
L
50 pF
t
PLZ
3-STATE Output
3.3
r
0.3
10.2
14.0
1.0
16.0
ns
R
L
1 k
:
C
L
50 pF
t
PHZ
Disable Time
5.0
r
0.5
6.1
8.8
1.0
10.0
C
L
50 pF
t
OSLH
Output to Output Skew
3.3
r
0.3
1.5
1.5
ns
(Note 4)
C
L
50 pF
t
OSHL
5.0
r
0.5
1.0
1.0
C
L
50 pF
f
MAX
Maximum Clock Frequency 3.3
r
0.3
80
130
70
MHz
C
L
15 pF
55
85
50
C
L
50 pF
5.0
r
0.5
130
185
110
C
L
15 pF
85
120
75
C
L
50 pF
C
IN
Input Capacitance
4
10
10
pF
V
CC
Open
C
OUT
Output Capacitance
6
pF
V
CC
5.0V
C
PD
Power Dissipation
32
pF
(Note 5)
Capacitance
Symbol
Parameter
V
CC
T
A
25
q
C
T
A
40
q
C to
85
q
C
Units
(V)
Min
Typ
Max
Min
Max
t
W
(H)
Minimum Pulse Width (CP)
3.3
r
0.3
5.0
5.5
ns
t
W
(L)
5.0
r
0.5
5.0
5.0
t
S
Minimum Set-Up Time
3.3
r
0.3
4.5
4.5
ns
5.0
r
0.5
3.0
3.0
t
H
Minimum Hold Time
3.3
r
0.3
2.0
2.0
ns
5.0
r
0.5
2.0
2.0
5
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7
4
VH
C37
4
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
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