August 1993
Revised April 1999
7
4
VH
C59
5
8-
Bit
Shi
f
t
Regi
st
er
w
i
th
Outpu
t
Latches
1999 Fairchild Semiconductor Corporation
DS011640.prf
www.fairchildsemi.com
74VHC595
8-Bit Shift Register with Output Latches
General Description
The VHC595 is an advanced high-speed CMOS Shift Reg-
ister fabricated with silicon gate CMOS technology. It
achieves the high-speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low
power dissipation.
This device contains an 8-bit serial-in, parallel-out shift reg-
ister that feeds an 8-bit D-type storage register. The stor-
age register has eight 3-STATE outputs. Separate clocks
are provided for both the shift register and the storage reg-
ister. The shift register has a direct-overriding clear, serial
input, and serial output (standard) pins for cascading. Both
the shift register and storage register use positive-edge
triggered clocks. If both clocks are connected together, the
shift register state will always be one clock pulse ahead of
the storage register.
An input protection circuit insures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
s
High Speed: t
PD
=
5.4 ns (typ) at V
CC
=
5V
s
Low power dissipation: I
CC
=
4
A (max) at T
A
=
25
C
s
High noise immunity: V
NIH
=
V
NIL
=
28% V
CC
(min)
s
Power down protection is provided on all inputs
s
Low noise: V
OLP
=
0.9V (typ)
s
Pin and function compatible with 74HC595
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Order Number
Package Number
Package Description
74VHC595M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74VHC595SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC595MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC595N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
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2
74
V
HC595
Pin Descriptions
Truth Table
Timing Diagram
Pin Names
Description
SER
Serial Data Input
SCK
Shift Register Clock Input
(Active rising edge)
RCK
Storage Register Clock Input
(Active rising edge)
SCLR
Reset Input
G
3-STATE Output Enable Input
(Active LOW)
Q
A
- Q
H
Parallel Data Outputs
Q'
H
Serial Data Output
Inputs
Function
SER RCK SCK SCLR G
X
X
X
X
H Q
A
thru Q
H
3-STATE
X
X
X
X
L Q
A
thru Q
H
outputs enabled
X
X
X
L
L Shift Register cleared
Q
H
= 0
L
X
H
L Shift Register clocked
Q
N
=
Q
n-1
, Q
0
=
SER
=
L
H
X
H
L Shift Register clocked
Q
N
=
Q
n-1
, Q
0
=
SER
=
H
X
X
H
L Contents of Shift
Register transferred to
output latches
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4
74
V
HC595
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
(Note 2)
Note 1: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Noise Characteristics
Note 3: Parameter guaranteed by design.
Supply Voltage (V
CC
)
-
0.5V to
+
7.0V
DC Input Voltage (V
IN
)
-
0.5V to
+
7.0V
DC Output Voltage (V
OUT
)
-
0.5V to V
CC
+
0.5V
Input Diode Current (I
IK
)
-
20 mA
Output Diode Current (I
OK
)
20 mA
DC Output Current (I
OUT
)
25 mA
DC V
CC
/GND Current (I
CC
)
75 mA
Storage Temperature (T
STG
)
-
65
C to
+
150
C
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
C
Supply Voltage (V
CC
)
2.0V to
+
5.5V
Input Voltage (V
IN
)
0V to
+
5.5V
Output Voltage (V
OUT
)
0V to V
CC
Operating Temperature (T
OPR
)
-
40
C to
+
85
C
Input Rise and Fall Time (t
r
, t
f
)
V
CC
=
3.3V
0.3V
0
100 ns/V
V
CC
=
5.0V
0.5V
0
20 ns/V
Symbol
Parameter
V
CC
(V)
T
A
=
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
Min
Typ
Max
Min
Max
V
IH
HIGH Level
2.0
1.50
1.50
V
Input Voltage
3.0
-
5.5
0.7 V
CC
0.7 V
CC
V
IL
LOW Level
2.0
0.50
0.50
V
Input Voltage
3.0
-
5.5
0.3 V
CC
0.3 V
CC
V
OH
HIGH Level
2.0
1.9
2.0
1.9
V
IN
=
V
IH
I
OH
=
-
50
A
Output Voltage
3.0
2.9
3.0
2.9
V
or V
IL
4.5
4.4
4.5
4.4
3.0
2.58
2.48
V
I
OH
=
-
4 mA
4.5
3.94
3.80
I
OH
=
-
8 mA
V
OL
LOW
Level 2.0
0.0
0.1
0.1
V
IN
=
V
IH
I
OL
=
50
A
Output Voltage
3.0
0.0
0.1
0.1
V
or V
IL
4.5
0.0
0.1
0.1
3.0
0.36
0.44
V
I
OL
=
4 mA
4.5
0.36
0.44
I
OL
=
8 mA
I
OZ
3-STATE
5.5
0.25
2.5
A
V
IN
=
V
CC
or GND
Output
V
OUT
=
V
CC
or GND
Off-State
V
IN
G
=
V
IH
or V
IL
Current
I
IN
Input Leakage Current
0
-
5.5
0.1
1.0
A
V
IN
=
5.5V or GND
I
CC
Quiescent Supply Current
5.5
4.0
40.0
A
V
IN
=
V
CC
or GND
Symbol
Parameter
V
CC
(V)
T
A
=
25
C
Units
Conditions
Typ
Limits
V
OLP
Quiet Output Maximum
5.0
0.9
1.2
V
C
L
=
50 pF
(Note 3)
Dynamic V
OL
V
OLV
Quiet Output Minimum
5.0
-
0.9
-
1.2
V
C
L
=
50 pF
(Note 3)
Dynamic V
OL
V
IHD
Minimum HIGH Level
5.0
3.5
V
C
L
=
50 pF
(Note 3)
Dynamic Input Voltage
V
ILD
Maximum LOW Level
5.0
1.5
V
C
L
=
50 pF
(Note 3)
Dynamic Input Voltage
5
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7
4
VH
C59
5
AC Electrical Characteristics
Note 4: Parameter guaranteed by design. t
OSLH
=
| t
PLH
max
-
t
PLH
min|; t
OSHL
=
| t
PHL
max
-
t
PHL
min|.
Note 5: C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained by the equation: I
CC
(opr.)
=
C
PD
* V
CC
* f
IN
+
I
CC
.
Symbol
Parameter
V
CC
(V)
T
A
=
+
25
C
T
A
=
-
40
C to
+
85
C
Units
Conditions
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay Time
3.3
0.3
7.7
11.9
1.0
13.5
ns
C
L
=
15 pF
t
PHL
RCK to Q
A
Q
H
10.2
15.4
1.0
17.0
C
L
=
50 pF
5.0
0.5
5.4
7.4
1.0
8.5
ns
C
L
=
15 pF
6.9
9.4
1.0
10.5
C
L
=
50 pF
t
PLH
Propagation Delay Time
3.3
0.3
8.8
13.0
1.0
15.0
ns
C
L
=
15 pF
t
PHL
SCKQ'H
11.3
16.5
1.0
18.5
C
L
=
50 pF
5.0
0.5
6.2
8.2
1.0
9.4
ns
C
L
=
15 pF
7.7
10.2
1.0
11.4
C
L
=
50 pF
t
PHL
Propagation Delay Time
3.3
0.3
8.4
12.8
1.0
13.7
ns
C
L
=
15 pF
SCLR Q'H
10.9
16.3
1.0
17.2
C
L
=
50 pF
5.0
0.5
5.9
8.0
1.0
9.1
ns
C
L
=
15 pF
7.4
10.0
1.0
11.1
C
L
=
50 pF
t
PZL
Output Enable Time
3.3
0.3
7.5
11.5
1.0
13.5
ns
R
L
=
1 k
C
L
=
15 pF
t
PZH
G to Q
A
Q
H
9.0
15.0
1.0
17.0
C
L
=
50 pF
5.0
0.5
4.8
8.6
1.0
10.0
ns
C
L
=
15 pF
8.3
10.6
1.0
12.0
C
L
=
50 pF
t
PLZ
Output Disable Time
3.3
0.3
12.1
15.7
1.0
16.2
ns
R
L
=
1 k
C
L
=
50 pF
t
PHZ
G to Q
A
Q
H
5.0
0.5
7.6
10.3
1.0
11.0
C
L
=
50 pF
f
MAX
Maximum Clock
3.3
0.3
80
150
70
MHz
C
L
=
15 pF
Frequency
55
130
50
C
L
=
50 pF
5.0
0.5
135
185
115
MHz
C
L
=
15 pF
95
155
85
C
L
=
50 pF
t
OSLH
Output to Output
3.3
0.3
1.5
1.5
ns
(Note 4)
C
L
=
50 pF
t
OSHL
Skew
5.0
0.5
1.0
1.0
C
L
=
50 pF
C
IN
Input Capacitance
5.0
10
10
pF
V
CC
=
Open
C
OUT
Output Capacitance
6.0
pF
V
CC
=
5.0V
C
PD
Power Dissipation
87
pF
(Note 5)
Capacitance
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