2005 Fairchild Semiconductor Corporation
DS011505
www.fairchildsemi.com
October 1992
Revised February 2005
7
4
VH
C74
Dual
D-
T
y
pe Fl
ip-
F
l
op wi
th
Preset
an
d Cl
ear
74VHC74
Dual D-Type Flip-Flop with Preset and Clear
General Description
The VHC74 is an advanced high speed CMOS Dual D-
Type Flip-Flop fabricated with silicon gate CMOS technol-
ogy. It achieves the high speed operation similar to equiva-
lent Bipolar Schottky TTL while maintaining the CMOS low
power dissipation. The signal level applied to the D input is
transferred to the Q output during the positive going transi-
tion of the CK pulse. CLR and PR are independent of the
CK and are accomplished by setting the appropriate input
LOW.
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Features
s
High Speed: f
MAX
170 MHz (typ) at T
A
25
q
C
s
High noise immunity: V
NIH
V
NIL
28% V
CC
(min)
s
Power down protection is provided on all inputs
s
Low power dissipation: I
CC
2
P
A (max) at T
A
25
q
C
s
Pin and function compatible with 74HC74
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Pb-Free package per JEDED J-STD-020B.
Note 1: "_NL" indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Order Number
Package
Package Description
Number
74VHC74M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VHC74MX_NL
M14A
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VHC74SJ
M14D
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC74MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC74MTCX_NL
(Note 1)
MTC14
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74VHC74N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
3
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7
4
VH
C74
Absolute Maximum Ratings
(Note 3)
Recommended Operating
Conditions
(Note 4)
Note 3: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading varai-
bles. Fairchild does not recommend operation outside databook specifica-
tions.
Note 4: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Supply Voltage (V
CC
)
0.5V to
7.0V
DC Input Voltage (V
IN
)
0.5V to
7.0V
DC Output Voltage (V
OUT
)
0.5V to V
CC
0.5V
Input Diode Current (I
IK
)
20 mA
Output Diode Current (I
OK
)
r
20 mA
DC Output Current (I
OUT
)
r
25 mA
DC V
CC
/GND Current (I
CC
)
r
50 mA
Storage Temperature (T
STG
)
65
q
C to
150
q
C
Lead Temperature (T
L
)
Soldering (10 seconds)
260
q
C
Supply Voltage (V
CC
)
2.0V to 5.5V
Input Voltage (V
IN
)
0V to
5.5V
Output Voltage (V
OUT
)
0V to V
CC
Operating Temperature (T
OPR
)
40
q
C to
85
q
C
Input Rise and Fall Time (t
r
, t
f
)
V
CC
3.3V
r
0.3V
0
a
100 ns/V
V
CC
5.0V
r
0.5V
0
a
20 ns/V
Symbol
Parameter
V
CC
(V)
T
A
25
q
C
T
A
40
q
C to
85
q
C
Units
Conditions
Min
Typ
Max
Min
Max
V
IH
HIGH Level Input
2.0
1.50
1.50
V
Voltage
3.0
5.5
0.7 V
CC
0.7 V
CC
V
IL
LOW Level Input
2.0
0.50
0.50
V
Voltage
3.0
5.5
0.3 V
CC
0.3 V
CC
V
OH
HIGH Level Output
2.0
1.9
2.0
1.9
V
IN
V
IH
I
OH
50
P
A
Voltage
3.0
2.9
3.0
2.9
V
or V
IL
4.5
4.4
4.5
4.4
3.0
2.58
2.48
V
I
OH
4 mA
4.5
3.94
3.80
I
OH
8 mA
V
OL
LOW Level Output
2.0
0.0
0.1
0.1
V
IN
V
IH
I
OL
50
P
A
Voltage
3.0
0.0
0.1
0.1
V
or V
IL
4.5
0.0
0.1
0.1
3.0
0.36
0.44
V
I
OL
4 mA
4.5
0.36
0.44
I
OL
8 mA
I
IN
Input Leakage Current
0
5.5
r
0.1
r
1.0
P
A
V
IN
5.5V or GND
I
CC
Quiescent Supply Current
5.5
2.0
20.0
P
A
V
IN
V
CC
or GND
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4
7
4
VH
C74
AC Electrical Characteristics
Note 5: C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained from the equation: I
CC
(opr.)
C
PD
* V
CC
* f
IN
I
CC
/2 (per F/F).
AC Operating Requirements
Note 6: V
CC
is 3.3
r
0.3V or 5.0
r
0.5V
Symbol
Parameter
V
CC
(V)
T
A
25
q
C
T
A
40
q
C to
85
q
C
Units
Conditions
Min
Typ
Max
Min
Max
f
MAX
Maximum Clock
3.3
r
0.3
80
125
70
MHz
C
L
15 pF
Frequency
50
75
45
C
L
50 pF
5.0
r
0.5
130
170
110
MHz
C
L
15 pF
90
115
75
C
L
50 pF
t
PLH
Propagation Delay
3.3
r
0.3
6.7
11.9
1.0
14.0
ns
C
L
15 pF
t
PHL
Time (CK-Q, Q)
9.2
15.4
1.0
17.5
C
L
50 pF
5.0
r
0.5
4.6
7.3
1.0
8.5
ns
C
L
15 pF
6.1
9.3
1.0
10.5
C
L
50 pF
t
PLH
Propagation Delay Time
3.3
r
0.3
7.6
12.3
1.0
14.5
ns
C
L
15 pF
t
PHL
(CLR, PR -Q, Q)
10.1
15.8
1.0
18.0
C
L
50 pF
5.0
r
0.5
4.8
7.7
1.0
9.0
ns
C
L
15 pF
6.3
9.7
1.0
11.0
C
L
50 pF
C
IN
Input Capacitance
4
10
10
pF
V
CC
Open
C
PD
Power Dissipation
25
pF
(Note 5)
Capacitance
Symbol
Parameter
V
CC
(V)
(Note 6)
T
A
25
q
C
T
A
40
q
C to
85
q
C
Units
Typ
Guaranteed Minimum
t
W
(L)
Minimum Pulse Width (CK)
3.3
6.0
7.0
ns
t
W
(H)
5.0
5.0
5.0
t
W
(L)
Minimum Pulse Width (CLR, PR)
3.3
6.0
7.0
ns
5.0
5.0
5.0
t
S
Minimum Setup Time
3.3
6.0
7.0
ns
5.0
5.0
5.0
t
H
Minimum Hold Time
3.3
0.5
0.5
ns
5.0
0.5
0.5
t
REC
Minimum Recovery Time (CLR, PR)
3.3
5.0
5.0
ns
5.0
3.0
3.0
5
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7
4
VH
C74
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
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