2005 Fairchild Semiconductor Corporation
DS500029
www.fairchildsemi.com
July 1997
Revised April 2005
7
4
VH
CT5
74A Oct
a
l
D-
T
ype Fl
ip
-Fl
op wi
th
3-ST
A
T
E Out
put
s
74VHCT574A
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The VHCT574A is an advanced high speed CMOS octal
flip-flop with 3-STATE output fabricated with silicon gate
CMOS technology. It achieves the high speed operation
similar to equivalent Bipolar Schottky TTL while maintain-
ing the CMOS low power dissipation. This 8-bit D-type flip-
flop is controlled by a clock input (CP) and an Output
Enable input (OE). When the OE input is HIGH, the eight
outputs are in a high impedance state.
Protection circuits ensure that 0V to 7V can be applied to
the input and output (Note 1) pins without regard to the
supply voltage. This device can be used to interface 3V to
5V systems and two supply systems such as battery back
up. This circuit prevents device destruction due to mis-
matched supply and input voltages.
Note 1: Outputs in OFF-State.
Features
s
High speed: f
MAX
140 MHz (typ) at T
A
25
q
C
s
Power Down Protection is provided on all inputs and
outputs.
s
Low Noise: V
OLP
1.6V (max)
s
Low Power Dissipation:
I
CC
4
P
A (max) @ T
A
25
q
C
s
Pin and Function Compatible with 74HCT574
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
IEEE/IEC
Connection Diagram
Order Number
Package Number
Package Description
74VHCT574AM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74VHCT574ASJ
M20D
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHCT574AMTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHCT574AN
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
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VH
CT57
4A
Pin Descriptions
Truth Table
H
HIGH Voltage Level
L
LOW Voltage Level
X
Immaterial
Z
High Impedance
LOW-to-HIGH Transition
Functional Description
The VHCT574A consists of eight edge-triggered flip-flops
with individual D-type inputs and 3-STATE true outputs.
The buffered clock and buffered Output Enable are com-
mon to all flip-flops. The eight flip-flops will store the state
of their individual D inputs that meet the setup and hold
time requirements on the LOW-to-HIGH Clock (CP) transi-
tion. With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. Opera-
tion of the OE input does not affect the state of the flip-
flops.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names
Description
D
0
D
7
Data Inputs
CP
Clock Pulse Input 3-STATE
OE
Output Enable Input 3-STATE
O
0
O
7
Outputs
Inputs
Outputs
D
n
CP
OE
O
n
H
L
H
L
L
L
X
X
H
Z
3
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Absolute Maximum Ratings
(Note 2)
Recommended Operating
Conditions
(Note 6)
Note 2: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
Note 3: HIGH or LOW state. I
OUT
absolute maximum rating must be
observed.
Note 4: When outputs are in OFF-State or when V
CC
OV.
Note 5: V
OUT
GND, V
OUT
!
V
CC
(Outputs Active).
Note 6: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Supply Voltage (V
CC
)
0.5V to
7.0V
DC Input Voltage (V
IN
)
0.5V to
7.0V
DC Output Voltage (V
OUT
)
(Note
3)
0.5V to V
CC
0.5V
(Note
4)
0.5V to
7.0V
Input Diode Current (I
IK
)
20 mA
Output Diode Current (I
OK
) (Note 5)
r
20 mA
DC Output Current (I
OUT
)
r
25 mA
DC V
CC
/GND Current (I
CC
)
r
75 mA
Storage Temperature (T
STG
)
65
q
C to
150
q
C
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
q
C
Supply Voltage (V
CC
)
4.5V to
5.5V
Input Voltage (V
IN
)
0V to
5.5V
Output Voltage (V
OUT
)
(Note 3)
0V to V
CC
(Note 4)
0V to
5.5V
Operating Temperature (T
OPR
)
40
q
C to
85
q
C
Input Rise and Fall Time (t
r
, t
f
)
V
CC
5.0V
r
0.5V
0 ns/V
a
20 ns/V
Symbol
Parameter
V
CC
T
A
25
q
C
T
A
40
q
C to
85
q
C
Units
Conditions
(V)
Min
Typ
Max
Min
Max
V
IH
HIGH Level
4.5
2.0
2.0
V
Input Voltage
5.5
2.0
20
V
IL
LOW Level
4.5
0.8
0.8
V
Input Voltage
5.5
0.8
0.8
V
OH
HIGH Level
4.5
4.40
4.50
4.40
V
V
IN
V
IH
I
OH
50
P
A
Output Voltage
3.94
3.80
V
or V
IL
I
OH
8 mA
V
OL
LOW Level
4.5
0.0
0.1
0.1
V
V
IN
V
IH
I
OL
50
P
A
Output Voltage
0.36
0.44
V
or V
IL
I
OL
8 mA
I
OZ
3-STATE Output
5.5
r
0.25
r
2.5
P
A
V
IN
V
IH
or V
IL
Off-State Current
V
OUT
V
CC
or GND
I
IN
Input Leakage
05.5
r
0.1
r
1.0
P
A
V
IN
5.5V or GND
Current
I
CC
Quiescent Supply
5.5
4.0
40.0
P
A
V
IN
V
CC
or GND
Current
I
CCT
Maximum I
CC
/Input
5.5
1.35
1.50
mA
V
IN
3.4V
Other Input
V
CC
or GND
I
OFF
Output Leakage Current
0.0
0.5
5.0
P
A
V
OUT
5.5V
(Power Down State)
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Noise Characteristics
Note 7: Parameter guaranteed by design.
AC Electrical Characteristics
Note 8: Parameter guaranteed by design. t
OSLH
|t
PLH max
t
PLH min
|; t
OSHL
|t
PHL max
t
PHL min
|
Note 9: C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained by the equation: I
CC
(opr.)
C
PD
* V
CC
* f
IN
I
CC
/8 (per F/F). The total C
PD
when n pcs. of the Octal D Flip-Flop operates
can be calculated by the equation: C
PD
(total)
20
12n.
AC Operating Requirements
Symbol
Parameter
V
CC
(V)
T
A
25
q
C
Units
Conditions
Typ
Limits
V
OLP
Quiet Output Maximum Dynamic V
OL
5.0
1.2
1.6
V
C
L
50 pF
(Note 7)
V
OLV
Quiet Output Minimum Dynamic V
OL
5.0
1.2
1.6
V
C
L
50 pF
(Note 7)
V
IHD
Minimum HIGH Level Dynamic Input Voltage
5.0
2.0
V
C
L
50 pF
(Note 7)
V
ILD
Maximum LOW Level Dynamic Input Voltage
5.0
0.8
V
C
L
50 pF
(Note 7)
Symbol
Parameter
V
CC
T
A
25
q
C
T
A
40
q
C to
85
q
C
Units
Conditions
(V)
Min
Typ
Max
Min
Max
t
PLH
Propagation Delay
5.0
r
0.5
4.1
9.4
1.0
10.5
ns
C
L
15 pF
t
PHL
Time
5.6
10.4
1.0
11.5
C
L
50 pF
t
PZL
3-STATE Output
5.0
r
0.5
6.5
10.2
1.0
11.5
ns
R
L
1 k
:
C
L
15 pF
t
PZH
Enable Time
7.3
11.2
1.0
12.5
C
L
50 pF
t
PLZ
3-STATE Output
5.0
r
0.5
7.0
11.2
1.0
12.0
ns
R
L
1 k
:
C
L
50 pF
t
PHZ
Disable Time
t
OSLH
Output to
5.0
r
0.5
1.0
1.0
ns
(Note 8)
t
OSHL
Output Skew
f
MAX
Maximum Clock
5.0
r
0.5
90
140
80
MHz
C
L
15 pF
Frequency
85
130
75
C
L
50 pF
C
IN
Input
4
10
10
pF
V
CC
Open
Capacitance
C
OUT
Output
9
pF
V
CC
5.0V
Capacitance
C
PD
Power Dissipation
25
pF
(Note 9)
Capacitance
Symbol
Parameter
V
CC
(V)
T
A
25
q
C
T
A
40
q
C to
85
q
C
Units
Min
Typ
Max
Min
Max
t
W
(H)
Minimum Pulse Width (CP)
5.0
r
0.5
6.5
8.5
ns
t
W
(L)
t
S
Minimum Set-Up Time
5.0
r
0.5
2.5
2.5
ns
t
H
Minimum Hold Time
5.0
r
0.5
2.5
2.5
5
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VH
CT5
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Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
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