1999 Fairchild Semiconductor Corporation
DS009584
www.fairchildsemi.com
March 1988
Revised August 1999
7
4F657
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74F657
Octal Bidirectional Transceiver with
8-Bit Parity Generator/Checker and 3-STATE Outputs
General Description
The 74F657 contains eight non-inverting buffers with 3-
STATE outputs and an 8-bit parity generator/checker. It is
intended for bus-oriented applications. The buffers have a
guaranteed current sinking capability of 24 mA at the A
Port and 64 mA at the B Port.
Features
s
300 Mil 24-pin slimline DIP
s
Combines 74F245 and 74F280A functions in one
package
s
3-STATE outputs
s
B Outputs sink 64 mA
s
12 mA source current, B side
s
Input diodes for termination effects
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number
Package Number
Package Description
75F657SC
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F657SPC
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
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2
74F657
Unit Loading/Fan Out
Functional Description
The Transmit/Receive (T/R) input determines the direction
of the data flow through the bidirectional transceivers.
Transmit (active HIGH) enables data from the A Port to the
B Port; Receive (active LOW) enables data from the B Port
to the A Port.
The Output Enable (OE) input disables the parity and
ERROR outputs and both the A and B Ports by placing
them in a HIGH-Z condition when the Output Enable input
is HIGH.
When transmitting (T/R HIGH), the parity generator detects
whether an even or odd number of bits on the A Port are
HIGH and compares these with the condition of the parity
select (ODD/EVEN). If the Parity Select is HIGH and an
even number of A inputs are HIGH, the Parity output is
HIGH.
In receiving mode (T/R LOW), the parity select and number
of HIGH inputs on port B are compared to the condition of
the Parity input. If an even number of bits on the B Port are
HIGH, the parity select is HIGH, and the PARITY input is
HIGH, then ERROR will be HIGH to indicate no error. If an
odd number of bits on the B Port are HIGH, the parity
select is HIGH, and the PARITY input is HIGH, the ERROR
will be LOW indicating an error.
Function Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Z
=
High Impedance
Function Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Pin Names
Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
A
0
A
7
Data Inputs/
4.5/0.15
90
A/
-
90
A
3-STATE Outputs
150/40 (33.3)
-
3 mA/24 mA (20 mA)
B
0
B
7
Data Inputs/
3.5/0.117
70
A/
-
70
A
3-STATE Outputs
600/106.6 (80)
-
12 mA/64 mA (48 mA)
T/R
Transmit/Receive Input
2.0/0.067
40
A/
-
40
A
OE
Enable Input
2.0/0.067
40
A/
-
40
A
PARITY
Parity Input/
3.5/0.117
70
A/
-
70
A
3-STATE Output
600/106.6 (80)
-
12 mA/64 mA (48 mA)
ODD/EVEN
ODD/EVEN Parity Input
1.0/0.033
20
A/
-
20
A
ERROR
Error Output
600/106.6 (80)
-
12 mA/64 mA (48 mA)
Number of
Inputs that
are HIGH
Inputs
Input/
Outputs
Output
OE T/R
ODD/
Parity ERROR
Outputs
EVEN
Mode
0, 2, 4, 6, 8
L
H
H
H
Z
Transmit
L
H
L
L
Z
Transmit
L
L
H
H
H
Receive
L
L
H
L
L
Receive
L
L
L
H
L
Receive
L
L
L
L
H
Receive
1, 3, 5, 7
L
H
H
L
Z
Transmit
L
H
L
H
Z
Transmit
L
L
H
H
L
Receive
L
L
H
L
H
Receive
L
L
L
H
H
Receive
L
L
L
L
L
Receive
Immaterial
H
X
X
Z
Z
Z
Inputs
Outputs
OE
T/R
L
L
Bus B Data to Bus A
L
H
Bus A Data to Bus B
H
X
High-Z State
3
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7
4F657
Functional Block Diagram
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4
74F657
Absolute Maximum Ratings
(Note 1)
Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Storage Temperature
-
65
C to
+
150
C
Ambient Temperature under Bias
-
55
C to
+
125
C
Junction Temperature under Bias
-
55
C to
+
150
C
V
CC
Pin Potential to Ground Pin
-
0.5V to
+
7.0V
Input Voltage (Note 2)
-
0.5V to
+
7.0V
Input Current (Note 2)
-
30 mA to
+
5.0 mA
Voltage Applied to Output
in HIGH State (with V
CC
=
0V)
Standard Output
-
0.5V to V
CC
3-STATE Output
-
0.5V to
+
5.5V
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
Free Air Ambient Temperature
0
C to
+
70
C
Supply Voltage
+
4.5V to
+
5.5V
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
V
IH
Input HIGH Voltage
2.0
V
Recognized as a HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized as a LOW Signal
V
CD
Input Clamp Diode Voltage
-
1.2
V
Min
I
IN
=
-
18 mA
V
OH
Output HIGH
10% V
CC
2.5
V
Min
I
OH
=
-
1 mA (A
n
)
Voltage
10% V
CC
2.4
I
OH
=
-
3 mA (A
n
B
n
, Parity, ERROR)
10% V
CC
2.0
I
OH
=
-
15 mA (B
n
, Parity, ERROR)
5% V
CC
2.7
I
OH
=
-
1 mA (A
n
)
5% V
CC
2.7
I
OH
=
-
3 mA (A
n
, B
n
, Parity, ERROR)
V
OL
Output LOW
10% V
CC
0.5
V
Min
I
OL
=
24 mA (A
n
)
Voltage
10% V
CC
0.55
I
OL
=
64 mA (B
n
Parity, ERROR)
I
IH
Input HIGH
20
A
Max
V
IN
=
2.7V (ODD/EVEN)
Current
40
V
IN
2.7V (T/R, OE)
I
BVI
Input HIGH Current
100
A
V
CC
=
0
V
IN
=
7.0V (T/R, OE, ODD/EVEN)
Breakdown Test
I
BVIT
Input HIGH Current
1.0
mA
Max
V
IN
=
5.5V (Parity, B
n
)
Breakdown Test (I/O)
2.0
V
IN
=
5.5V (A
n
)
I
IL
Input LOW
-
20
A
Max
V
IN
=
0.5V (ODD/EVEN)
Current
-
40
V
IN
=
0.5V (T/R, OE)
I
OZH
Output Leakage Current
50
A
Max
V
OUT
=
2.7V (ERROR)
I
OZL
Output Leakage Current
-
50
A
Max
V
OUT
=
0.5V (ERROR)
I
IH
+
I
OZH
Output Leakage
70
A
Max
V
I/O
=
2.7V (B
n
, Parity)
Current
90
V
I/O
=
2.7V (A
n
)
I
IL
+
I
OZL
Output Leakage
-
70
A
Max
V
I/O
=
0.5V (B
n
, Parity)
Current
-
90
V
I/O
=
0.5V (A
n
)
I
OS
Output Short-Circuit
-
60
-
150
mA
Max
V
OUT
=
0V (A
n
)
Current
-
100
-
225
V
OUT
=
0V (B
n
, Parity, ERROR)
I
CEX
Output HIGH Leakage
250
A
Max
V
OUT
=
V
CC
(ERROR)
Current
1.0
mA
Max
V
OUT
=
V
CC
(B
n
, Parity)
2.0
mA
Max
V
OUT
=
V
CC
(A
n
)
I
ZZ
Bus Drainage Test
500
A
0.0V
V
OUT
=
5.25V (A
n
, B
n
, Parity, ERROR)
I
CCH
Power Supply Current
101
125
mA
Max
V
O
=
HIGH
I
CCL
Power Supply Current
112
150
mA
Max
V
O
=
LOW
I
CCZ
Power Supply Current
109
145
mA
Max
V
O
=
HIGH Z
5
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7
4F657
AC Electrical Characteristics
Note 3: These delay times reflect the 3-STATE recovery time only and not the signal time through the buffers or the parity check circuity. To assure VALID
information at the ERROR pin, time must be allowed for the signal to propagate through the drivers (B to A), through the parity check circuitry (same as A to
PARITY), and to the ERROR output after the ERROR pin has been enabled (Output Enable times). VALID data at the ERROR pin
(A to PARITY)
+
(Output
Enable Time).
Symbol
Parameter
T
A
=
+
25
C
T
A
=
-
55
C to
+
125
C
T
A
=
0
C to
+
70
C
Units
V
CC
=
+
5.0V
V
CC
=
+
5.0V
V
CC
=
+
5.0V
C
L
=
50 pF
C
L
=
50 pF
C
L
=
50 pF
Min
Typ
Max
Min
Max
Min
Max
t
PLH
Propagation Delay
2.5
4.5
8.0
2.5
9.5
2.5
9.0
ns
t
PHL
A
n
to B
n
, B
n
to A
n
3.0
4.9
7.5
3.0
8.5
3.0
8.0
t
PLH
Propagation Delay
6.5
10.1
14.0
5.5
18.0
6.0
16.0
ns
t
PHL
A
n
to Parity
7.0
10.9
15.0
5.5
20.5
6.0
16.5
t
PLH
Propagation Delay
4.5
7.8
11.0
4.0
14.0
4.0
13.0
ns
t
PHL
ODD/EVEN to PARITY
4.5
8.8
12.0
4.5
16.5
4.5
13.5
t
PLH
Propagation Delay
4.5
7.5
11.0
4.0
14.0
4.0
13.0
ns
t
PHL
ODD/EVEN to ERROR
4.5
8.2
12.0
4.5
16.5
4.5
13.5
t
PLH
Propagation Delay
8.0
14.0
20.5
7.5
27.0
7.5
23.0
ns
t
PHL
B
n
to ERROR
8.0
15.0
21.5
7.5
28.5
7.5
23.5
t
PLH
Propagation Delay
7.0
10.8
15.5
6.0
20.0
6.0
17.0
ns
t
PHL
PARITY to ERROR
7.5
11.8
16.5
6.5
22.0
7.5
18.5
t
PZH
Output Enable Time
3.0
5.0
8.0
2.5
11.0
2.5
9.5
ns
t
PZL
OE to A
n
/B
n
4.0
6.5
10.0
3.5
13.5
3.5
11.0
t
PHZ
Output Disable Time
1.0
4.5
8.0
1.0
9.5
1.0
9.0
ns
t
PLZ
OE to A
n
/B
n
1.0
4.9
7.5
1.0
8.5
1.0
8.0
t
PZH
Output Enable Time
3.0
5.0
8.0
2.5
11.0
2.5
9.5
ns
t
PZL
OE to ERROR (Note 3)
4.0
7.7
10.0
3.5
13.5
3.5
11.0
t
PHZ
Output Disable Time
1.0
4.5
8.0
1.0
9.5
1.0
9.0
ns
t
PLZ
OE to ERROR
1.0
4.9
7.5
1.0
8.5
1.0
8.0
t
PZH
Output Enable Time
3.0
5.0
8.0
2.5
11.0
2.5
9.5
ns
t
PZL
OE to PARITY
4.0
7.7
10.0
3.5
13.5
3.5
11.0
t
PHZ
Output Disable Time
1.0
4.6
8.0
1.0
9.5
1.0
9.0
ns
t
PLZ
OE to PARITY
1.0
5.1
7.5
1.0
8.5
1.0
8.0
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