www.docs.chipfind.ru
2000 Fairchild Semiconductor Corporation
DS009172
www.fairchildsemi.com
October 1986
Revised February 2000
DM74ALS646 Octal
3-ST
A
T
E
Bus T
r
ansc
eiver
and
Regi
ster
DM74ALS646
Octal 3-STATE Bus Transceiver and Register
General Description
This device incorporates an octal bus transceiver and an
octal D-type register configured to enable multiplexed
transmission of data from bus to bus or internal register to
bus.
This bus transceiver features totem-pole 3-STATE outputs
designed specifically for driving highly-capacitive or rela-
tively low-impedance loads. The high-impedance state and
increased high-logic level drive provides this device with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without the need for
interface or pull-up components. They are particularly
attractive for implementing buffer registers, I/O ports, bidi-
rectional bus drivers, and working registers.
The registers in the DM74ALS646 are edge-triggered D-
type flip-flops. On the positive transition of the clock (CAB
or CBA), the input bus data is stored into the appropriate
register. The CAB input controls the transfer of data into
the A register and the CBA input controls the B register.
The SAB and SBA control pins are provided to select
whether real-time data or stored data is transferred. A LOW
input level selects real-time data, and a HIGH level selects
stored data. The select controls have a "make before
break" configuration to eliminate a glitch which would nor-
mally occur in a typical multiplexer during the transition
between store and real-time data.
The enable G and direction control pins provide four modes
of operation: real-time data transfer from bus A to B, real-
time data transfer from bus B to A, real-time bus A and/or B
data transfer to internal storage, or internally stored data
transfer to bus A or B.
When the enable G pin is LOW, the direction pin selects
which bus receives data. When the enable G pin is HIGH,
both buses become disabled yet their input function is still
enabled.
Features
s
Switching specifications at 50 pF
s
Switching specifications guaranteed over full tempera-
ture and V
CC
range
s
Advanced oxide-isolated, ion-implanted Schottky TTL
process
s
3-STATE buffer outputs drive bus lines directly
s
Multiplexed real-time and stored data
s
Independent registers for A and B buses
Ordering Code
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Order Number
Package Number
Package Description
DM74ALS646WM
M24B
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74ALS646NT
N24C
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
www.fairchildsemi.com
2
D
M
74ALS646
Connection Diagram
Function Table
H
=
HIGH Logic Level
L
=
LOW Logic Level
X
=
Don't Care (Either LOW or HIGH Logic Levels including transitions)
H/L
=
Either LOW or HIGH Logic Level excluding transitions
=
Positive going edge of pulse
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled, i.e., data
at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
Logic Diagram
Inputs
Data I/O (Note 1)
Operation or Function
G
DIR CAB CBA SAB SBA
A1 thru A8
B1 thru B8
X
X
X
X
X
Input
Not Specified Store A, B Unspecified
X
X
X
X
X
Not Specified
Input
Store B, A Unspecified
H
X
X
X
Input
Input
Store A and B Data
H
X
H/L
H/L
X
X
Input
Input
Isolation, Hold Storage
L
L
X
X
X
L
Output
Input
Real-Time B Data to a Bus
L
L
X
H/L
X
H
Output
Input
Stored B Data to a Bus
L
H
X
X
L
X
Input
Output
Real-Time A Data to B Bus
L
H
H/L
X
H
X
Input
Output
Stored A Data to B Bus
3
www.fairchildsemi.com
DM74ALS646
Absolute Maximum Ratings
(Note 2)
Note 2: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Recommended Operating Conditions
Note 3:
=
With reference to the LOW-to-HIGH transition of the respective clock.
Electrical Characteristics
over recommended free air temperature range
Note 4: For I/O ports the 3-STATE output currents (I
OZH
and I
OZL
) are included in the I
IH
and I
IL
parameters.
Supply Voltage
7V
Input Voltage
Control Inputs
7V
I/O Ports
5.5V
Operating Free-Air Temperature Range
0
C to
+
70
C
Storage Temperature Range
-
65
C to
+
150
C
Typical
JA
N Package
44.5
C/W
M Package
80.5
C/W
Symbol
Parameter
Min
Nom
Max
Units
V
CC
Supply Voltage
5
5.5
V
V
IH
HIGH Level Input Voltage
V
V
IL
LOW Level Input Voltage
0.8
V
I
OH
HIGH Level Output Current
-
15
mA
I
OL
LOW Level Output Current
24
mA
f
CLK
Clock Frequency
40
MHz
t
W
Pulse Duration, Clocks LOW or HIGH
ns
t
SU
Data Setup Time, A before CAB or B before CBA (Note 3)
10
ns
t
H
Data Hold Time, A after CAB or B after CBA (Note 3)
0
ns
T
A
Free Air Operating Temperature
70
C
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
V
IC
Input Clamp Voltage
V
CC
=
Min, I
I
=
-
18 mA
-
1.2
V
V
OH
HIGH Level
V
CC
=
4.5V to 5.5V
I
OH
=
-
0.4 mA
V
CC
-
2
Output Voltage
V
CC
=
Min
I
OH
=
-
3 mA
2.4
3.2
V
I
OH
=
Max
2
V
OL
LOW
Level V
CC
=
Min
I
OL
=
12 mA
0.25
0.4
Output Voltage
I
OL
=
24 mA
0.35
0.5
V
I
OL
=
48 mA
0.35
0.5
I
I
Input Current at Maximum
V
CC
=
Max
I/O Ports, V
I
=
5.5V
100
A
Input Voltage
Control Inputs, V
I
=
7V
100
I
IH
HIGH Level Input Current
V
CC
=
Max, V
I
=
2.7V (Note 4)
20
A
I
IL
LOW
Level V
CC
=
Max,
Control Inputs
-
200
A
Input Current
V
I
=
0.4V, (Note 4)
I/O Ports
-
200
I
O
Output Drive Current
V
CC
=
Max, V
O
=
2.25V
-
30
-
112
mA
I
CC
Supply Current
V
CC
=
Max
Outputs HIGH
47
76
Outputs LOW
55
88
mA
Outputs Disabled
55
88
www.fairchildsemi.com
4
D
M
74ALS646
Switching Characteristics
over recommended operating free air temperature range
Note 5: These parameters are measured with the internal output state of the storage register opposite to that of the bus input.
Symbol
Parameter
Conditions
From (Input)
Min
Max
Units
To (Output)
t
PLH
Propagation Delay Time
V
CC
=
4.5V to 5.5V,
CBA or CAB
10
30
ns
LOW-to-HIGH Level Output
C
L
=
50 pF,
to A or B
t
PHL
Propagation Delay Time
R
1
=
R
2
=
500
,
CBA or CAB
5
17
ns
HIGH-to-LOW Level Output
T
A
=
Min to Max
to A or B
t
PLH
Propagation Delay Time
A or B to
5
20
ns
LOW-to-HIGH Level Output
B or A
t
PHL
Propagation Delay Time
A or B to
3
12
ns
HIGH-to-LOW Level Output
B or A
t
PLH
Propagation Delay Time
SBA or SAB
LOW-to-HIGH Level Output
to A or B
12
35
ns
(with A or B LOW) (Note 5)
t
PHL
Propagation Delay Time
SBA or SAB
HIGH-to-LOW Level Output
to A or B
5
20
ns
(with A or B LOW) (Note 5)
t
PLH
Propagation Delay Time
SBA or SAB
LOW-to-HIGH Level Output
to A or B
6
25
ns
(with A or B HIGH) (Note 5)
t
PHL
Propagation Delay Time
SBA or SAB
HIGH-to-LOW Level Output
to A or B
5
20
ns
(with A or B HIGH) (Note 5)
t
PZH
Output Enable Time
G to
3
17
ns
to HIGH Level Output
A or B
t
PZL
Output Enable Time
G to
5
20
ns
to LOW Level Output
A or B
t
PHZ
Output Disable Time
G to
1
10
ns
from HIGH Level Output
A or B
t
PLZ
Output Disable Time
G to
2
16
ns
from LOW Level Output
A or B
t
PZH
Output Enable Time
DIR to
6
30
ns
to HIGH Level Output
A or B
t
PZL
Output Enable Time
DIR to
5
25
ns
to LOW Level Output
A or B
t
PHZ
Output Disable Time
DIR to
1
10
ns
from HIGH Level Output
A or B
t
PLZ
Output Disable Time
DIR to
2
16
ns
from LOW Level Output
A or B
5
www.fairchildsemi.com
DM74ALS646
Physical Dimensions
inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M24B
PDF 
ZIP