2000 Fairchild Semiconductor Corporation
DS006305
www.fairchildsemi.com
October 1986
Revised April 2000
DM74AS286
9-
B
i
t
Pari
ty
Gener
a
tor
/
Checker
wi
th
Bus-Dr
iver
Par
i
t
y
I
/
O
Port
DM74AS286
9-Bit Parity Generator/Checker
with Bus-Driver Parity I/O Port
General Description
These universal, 9-bit parity generators/checkers utilize
advanced Schottky high performance circuitry and feature
odd/even outputs to facilitate operation of either odd or
even parity applications. The word length capability is eas-
ily expanded by cascading.
The DM74AS286 can be used to upgrade the performance
of most systems utilizing the DM74AS280 parity generator/
checker. Although the DM74AS286 is implemented without
expander inputs, the corresponding function is provided by
the availability of an input pin XMIT. XMIT is a control line
which makes parity error output active and parity an input
port when HIGH; when LOW, parity error output is inactive
and parity becomes an output port. In addition, parity I/O
control circuitry contains a feature to keep the I/O port in
the 3-STATE during power UP or DOWN to prevent bus
glitches.
Features
s
PNP inputs to reduce bus loading
s
Generates either odd or even parity for nine data lines
s
Inputs are buffered to lower the drive requirements
s
Can be used to upgrade existing systems using MSI
parity circuits
s
Cascadable for n-bits
s
Switching specifications at 50 pF
s
Switching specifications guaranteed over full
temperature and V
CC
range
s
A parity I/O portable to drive bus
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Function Table
L
=
LOW Logic Level
H
=
HIGH Logic Level
N/A
=
Not Applicable
Order Number
Package Number
Package Description
DM74AS286M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74AS286N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Number of Inputs
Parity I/O
XMIT
Parity
Error
Mode
(A thru I)
of
that are HIGH
Input Output
Operation
0, 2, 4, 6, 8
N/A
H
L
H
Parity
1, 3, 5, 7, 9
N/A
L
L
H
Generator
0, 2, 4, 6, 8
H
N/A
H
H
Parity
0, 2, 4, 6, 8
L
N/A
H
L
Checker
1, 3, 5, 7, 9
H
N/A
H
L
Parity
1, 3, 5, 7, 9
L
N/A
H
H
Checker
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2
DM
74AS286
Absolute Maximum Ratings
(Note 1)
Note 1: The "Absolute Maximum Ratings" are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The "Recommended Operating Conditions" table will define the conditions
for actual device operation.
Recommended Operating Conditions
Electrical Characteristics
over recommended free-air temperature range. All typical values are measured at V
CC
=
5V, T
A
=
25
C.
Note 2: For I/O ports, the parameters I
IH
and I
IL
include the OFF-state current, I
OZH
and I
OZL
.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
0
C to
+
70
C
Storage Temperature Range
-
65
C to
+
150
C
Typical
JA
N Package
77.0
C/W
M Package
108.0
C/W
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Supply Voltage
4.5
5
5.5
V
V
IH
HIGH Level Input Voltage
2
V
V
IL
LOW Level Input Voltage
0.8
V
I
OH
HIGH Level Output Current
Parity I/O
-
15
mA
Parity Error
-
2
mA
I
OL
LOW Level Output Current
Parity I/O
48
mA
Parity Error
20
mA
T
A
Operating Free-Air Temperature
0
70
C
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
IK
Input Clamp Voltage
V
CC
=
4.5V, I
IN
=
-
18 mA
-
1.2
V
V
OH
HIGH Level
I
OH
=
Max, V
CC
=
4.5V
2.4
3.2
V
Output Voltage
V
CC
=
4.5V to 5.5V, I
OH
=
-
2 mA
V
CC
-
2
V
V
OL
LOW Level Output Voltage
V
CC
=
4.5V, I
OL
=
Max
0.35
0.5
V
I
I
Input Current at Maximum
V
CC
=
5.5V, V
IH
=
7V
0.1
mA
Input Voltage
(V
I
=
5.5V for Parity I/O)
I
IH
HIGH Level Input Current
V
CC
=
5.5V
Others
20
A
V
IH
=
2.7V (Note 2)
Parity I/O
50
I
IL
LOW Level Input Current
V
CC
=
5.5V, V
IL
=
0.4V (Note 2)
-
0.5
mA
I
O
Output Drive Current
V
CC
=
5.5V, V
OUT
=
2.25V
-
30
-
112
mA
I
CC
Supply Current
V
CC
=
5.5V, Transmit Mode
43
mA
XMIT
=
LOW
Receive Mode
50
mA
XMIT
=
HIGH
3
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DM74AS286
Switching Characteristics
over recommended supply and temperature range
Typical Applications
FIGURE 1. Dedicated 10-Bit Parity Sensing Configuration
Symbol
Parameter
From
To
Min
Max
Units
t
PLH
Propagation Delay Time
Any Data Input
Parity I/O
3
15
ns
from LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
Any Data Input
Parity I/O
3
14
ns
from HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
Any Data Input
Parity Error
3
16.5
ns
from LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
Any Data Input
Parity Error
3
16.5
ns
from HIGH-to-LOW Level Output
t
PLH
Propagation Delay Time
Parity I/O
Parity Error
3
9
ns
from LOW-to-HIGH Level Output
t
PHL
Propagation Delay Time
Parity I/O
Parity Error
3
9
ns
from HIGH-to-LOW Level Output
t
PZL
Output Enable Time to LOW Level
XMIT
Parity I/O
3
16
ns
t
PLZ
Output Disable Time from LOW Level
XMIT
Parity I/O
3
10
ns
t
PZH
Output Disable Time from HIGH Level
XMIT
Parity I/O
3
13
ns
t
PHZ
Output Enable Time to HIGH Level
XMIT
Parity I/O
3
11.5
ns
Number of
Parity
Inputs that
Result
are Logic "1"
Output
0, 2, 4, 6, 8, 10
Even
L
1, 3, 5, 7, 9
Odd
H
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4
DM
74AS286
Typical Applications
(Continued)
L
=
LOW Logic Level
H
=
HIGH Logic Level
N/A
=
Not Applicable
FIGURE 2. Bus I/O Parity Implementation
Direction
I/O
Parity Check Result
Control
Direction
(Parity Error)
(XMIT)
(Parity I/O)
Level
Result
H
Input
H
True
(Receive)
L
False
L
Output
H
N/A
(Transmit)
Parity Select
(Input I)
Level
Format
H
Even
L
Odd
5
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DM74AS286
Typical Applications
(Continued)
Note: Parity format in this configuration is "odd parity"
FIGURE 3. 90-Bit Parity Generator/Checker Implementation
Using Device Expansion Techniques
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