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Электронный компонент: FAN5019

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www.fairchildsemi.com
REV. 1.0.7 1/5/04
Features
Pin and Function Backward Compatible with FAN53168
and FAN53180 Controllers
Precision Multi-Phase DC-DC Core Voltage Regulation
10mV Output Voltage Accuracy Over Temperature
Differential Remote Voltage Sensing
Selectable 2, 3, or 4 Phase Operation
Selectable VRM9 or VRM10 Operation
Up to 1MHz per Phase Operation (4MHz ripple
Frequency)
Lossless Inductor Current Sensing for Loadline
Compensation
External Temperature Compensation
Accurate Load-Line Programming (Meets Intel
VRM/VRD10.0 and 10.X CPU Specifications)
Accurate Channel-Current Balancing for Thermal
Optimization and Layout Compensation
Convenient 12V Supply Biasing
6-bit Voltage Identification (VID) Input
.8375V to 1.600V in 12.5mV Steps
Dynamic VID Capability with Fault-Blanking for
glitch-less Output voltage Changes
Adjustable Over Current Protection with Programmable
Latch-Off Delay. Latch-Off Function may be Disabled
Over-Voltage Protection Internal OVP Crowbar
Protection
Applications
Computer DC/DC Converter VRM/VRD10.0
Computer DC/DC Converter VRM/VRD10.X
Computer DC/DC Converter VRM/VRD9.X
High Current, Low Voltage DC/DC Rail
General Description
The FAN5019 is a multi-phase DC-DC controller for imple-
menting high-current, low-voltage, CPU core power regula-
tion circuits. It is part of a chipset that includes external
MOSFET drivers and power MOSFETS. The FAN5019
drives up to four synchronous-rectified buck channels in par-
allel. The multi-phase buck converter architecture uses inter-
leaved switching to multiply ripple frequency by the number
of phases and reduce input and output ripple currents. Lower
ripple results in fewer components, lower component cost,
reduced power dissipation, and smaller board area.
The FAN5019 features a high bandwidth control loop to
provide optimal response to load transients. The FAN5019
senses current using lossless techniques: Phase current is
measured through each of the output inductors. This current
information is summed, averaged and used to set the loadline
of the output via programmable "droop". The droop is tem-
perature compensated to achieve precise loadline character-
istics over the entire operating range. Additionally,
individual phase current is measured using the R
DS(ON)
of
the low-side MOSFETs. This information is used to dynam-
ically balance/steer per-phase current. The phase currents
are also summed and averaged for over-current detection.
Dynamic-VID technology allows on-the-fly VID changes
with controlled, glitch-less output. Additionally, short-circuit
protection, adjustable current limiting, over-voltage protec-
tion and power-good circuitry combine to ensure reliable and
safe operation. The operating temperature range is 0C to
+85C and the operating voltage is a single +12V supply,
which simplifies the design. The FAN5019 is available in a
TSSOP-28 package.
Block Diagram
FAN5019
V
IN
V
IN
1
4
V
OUT
3
2
FAN5009
FAN5009
FAN5019
6-Bit VID Controller 2-4 Phase VRM10.X Controller
FAN5019
PRODUCT SPECIFICATION
2
REV. 1.0.7 1/5/04
Pin Assignments
Pin Definitions
Pin Number
Pin Name
Pin Function Description
15
VID [4:0]
VID inputs. Determines the output voltage via the internal DAC. These inputs
comply to VRM10/VRD10 specifications for static and dynamic operation. All have
internal pull-ups (1.25V for VRM10 and 2.5V for VRM9) so leaving them open
results in logic high. Leaving VID[4:0] open results in a "No CPU" condition
disabling the PWM outputs.
6
VID5/SEL
VID5 Input/DAC Select. Dual function pin that is either the 12.5mV DAC LSB for
VRM10 or selects the VRM9 DAC codes when forced higher than Vtblsel(VRM9)
voltage. The truth table is as follows:
V
VID5/SEL
held > Vtblsel(VRM9); VRM9 DAC table is selected (See Table 3)
V
ViD5/SEL
< Vtblsel(VRM10); VRM10 DAC table is selected (See Table 2) and
V
ViD5/SEL
pin is used as VID5 input.
7
FBRTN
Feedback Return. Error Amp and DAC reference point.
8
FB
Feedback Input. Inverting input for Error Amp this pin is used for external
compensation. This pin can also be used to introduce DC offset voltage to the
output.
9
COMP
Error Amp output. This pin is used for external compensation.
10
PWRGD
Power Good output. This is an open-drain output that asserts when the output
voltage is within the specified tolerance. It is expected to be pulled up to an external
voltage rail.
11
EN
Enable. Logic signal that enables the controller when logic high.
12
DELAY
Soft-start and Current Limit Delay. An external resistor and capacitor sets the
softstart ramp rate and the over-current latch off delay.
13
RT
Switching Frequency Adjust. This pin adjusts the output PWM switching
frequency via an external resistor.
14
RAMPADJ
PWM Current Ramp Adjust. An external resistor to Vcc will adjust the amplitude of
the internal PWM ramp.
15
ILIMIT
Current Limit Adjust. An external resistor sets the current limit threshold for the
regulator circuit. This pin is internally pulled low when EN is low or the UVLO circuit
is active. It is also used to enable the drivers.
DELAY
VID4
VID3
VID2
VID1
VID0
COMP
CSCOMP
PWRGD
EN
CSSUM
RT
VCC
SW2
SW3
PWM3
PWM4
PWM1
GND
FBRTN
ILIMIT
FB
CSREF
RAMPADJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
FAN5019
TSSOP-28
SW1
PWM2
SW4
VID5/SEL
PRODUCT SPECIFICATION
FAN5019
REV. 1.0.7 1/5/04
3
16
CSREF
Current Sense Reference. Non-Inverting input of the current sense amp. Sense
point for the output voltage used for OVP and PWRGD.
17
CSSUM
Current Sense Summing node. Inverting input of the current sense amp.
18
CSCOMP
Current Sense Compensation node. Output of the current sense amplifier. This
pin is used, in conjunction with CSSUM to set the output droop compensation and
current loop response.
19
GND
Ground. Signal ground for the device.
2023
SW[4:1]
Phase Current Sense/Balance inputs. Phase-to-phase current sense and
balancing inputs. Unused phases should be left open.
2427
PWM[4:1]
PWM outputs. CMOS outputs for driving external gate drivers such as the
FAN53418 or FAN5009. Unused phases should be grounded.
28
VCC
Chip Power. Bias supply for the chip. Connect directly to a +12V supply. Bypass
with a 1F MLCC capacitor.
Pin Definitions
(continued)
Pin Number
Pin Name
Pin Function Description
FAN5019
PRODUCT SPECIFICATION
4
REV. 1.0.7 1/5/04
Absolute Maximum Ratings
Absolute maximum ratings are the values beyond which the device may be damaged or have its useful life
impaired. Functional operation under these conditions is not implied.
Thermal Information
Recommended Operating Conditions
(See Figure 8)
Note:
1:
JA
is defined as 1 oz. copper PCB with 1 in
2
pad.
Parameter
Min.
Max.
Units
Supply Voltage: VCC to GND
-0.3
+15
V
Voltage on FBRTN pin
-0.3
+0.3
V
Voltage on SW1-SW4 (<250ns duration)
-5
+25
V
Voltage on SW1-SW4 (>=250ns duration)
-0.3
+15
V
Voltage on RAMPADJ, CSSUM
-0.3
VCC+0.3
V
Voltage on any other pin
-0.3
+5.5
V
Parameter
Min.
Typ
Max.
Units
Operating Junction Temperature (T
J
)
0
+150
C
Storage Temperature
65
+150
C
Lead Soldering Temperature, 10 seconds
+300
C
Vapor Phase, 60 seconds
+215
C
Infrared, 15 seconds
+220
C
Power Dissipation (P
D
) @ T
A
= 25C
2
W
Thermal Resistance (
JA
)*
50
C/W
Parameter
Conditions
Min.
Typ.
Max.
Units
Supply Voltage VCC
VCC to GND
10.2
12
13.8
V
Ambient Operating Temperature
0
+85
C
Operating Junction Temperature (T
J
)
0
+125
PRODUCT SPECIFICATION
FAN5019
REV. 1.0.7 1/5/04
5
Electrical Specifications
(V
CC
= 12V, T
A
= 0C to +85C and FBRTN=GND, using circuit in Figure 1, unless otherwise noted.)
The
denotes specifications which apply over the full operating temperature range.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Error Amplifier
Output Voltage Range
V
COMP
0.5
3.5
V
Accuracy
V
FB
Relative to DAC Setting,
referenced to FBRTN,
CSSUM = CSCOMP,
Test Circuit 3
VRM10
VRM9
-10
-12
+10
+12
mV
Line Regulation
V
FB
VCC=10V to 14V
0.05
%
Input Bias Current
I
FB
-13
-15
-17
A
FBRTN Current
I
FBRTN
150
180
A
Output Current
I
O(ERR)
FB forced to V
OUT
3%
300
500
A
Gain Bandwidth Product
GBW
COMP = FB
20
MHz
DC Gain
C
COMP
= 10pF
77
dB
VID Inputs
Input Low Voltage
V
IL(VID)
VRM10
VRM9
0.4
0.8
V
V
Input High Voltage
V
IH(VID)
VRM10
VRM9
0.8
2.0
V
V
Input Current, VID Low
I
IL(VID)
VID(X) = 0V
-30
-20
A
Input Current, VID High
I
IH(VID)
VID(X) = 1.25V
-2
2
A
Pull-up Resistance
R
VID
Internal
35
60
115
k
Internal Pull-up Voltage
VRM10
VRM9
1.0
2.2
1.15
2.4
1.26
2.6
V
V
VID Transition Delay Time
2
VID Code Change to FB Change
400
ns
"No CPU" Detection
Turn-off Delay Time
2
VID Code Change to 11111X to PWM
going low
400
ns
VID Table Select
Vtblsel
To select VRM9 table
To select VRM10 table (becomes VID5)
4
3.5
V
V
Oscillator
Frequency
f
OSC
200
4000
kHz
Frequency Variation
f
PHASE
T
A
= +25C, R
T
= 250k
, 4-Phase
T
A
= +25C, R
T
= 115k
, 4-Phase
T
A
= +25C, R
T
= 75k
, 4-Phase
155
200
400
600
245
kHz
kHz
kHz
Output Voltage
V
RT
R
T
= 100k
to GND
1.9
2.0
2.1
V
RAMPADJ Pin Accuracy
V
RAMPADJ
V
RAMPADJ
= Vdac = +2K (VinVdac)/
(Rr+2k)
-50
+50
mV
RAMPADJ Input Current
I
RAMPADJ
Current into RAMPADJ pin
0
100
A
Current Sense Amplifier
Offset Voltage
V
OS(CSA)
CSSUMCSREF, Test Circuit 1
-1.5
+1.5
mV
Input Bias Current
I
BIAS(CSA)
-50
+50
nA
Gain Bandwidth Product
GBW
COMP = FB
10
MHz
Notes:
1. All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control
2. Guaranteed by design NOT tested in production.